Lluís Terés

xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures

This paper describes xENoC, an automatic and component re-use HW-SW environment to build simulatable and synthesizable Network-on-Chip-based MPSoC architectures. xENoC is based on a tool, named NoCWizard, which uses an eXtensible Markup Language (XML) specification, and a set of modularized components and templates to generate many types of NoC instances by using Verilog HDL. This NoC models can be customized in terms of topology, tile location/mapping, RNIs generation, different types of routers, FIFO and packet/flit sizes, by simply modifying the XML specifications. Furthermore, xENoC is also composed of software components, i.e. RNI drivers and a parallel programming model, embedded Message Passing Interface (eMPI), which let us to carry out a complete HW-SW co-design methodology to design distributed-memory NoC-based MPSoCs parallel applications. Through xENoC different distributed-memory NoC-based MPSoCs designs have been created simulated and prototyped in physical platforms (e.g. FPGA boards), and some parallel multiprocessor test traffic applications are running there as system level demonstrators.

Low-Power and Compact CMOS APS Circuits for Hybrid Cryogenic Infrared Fast Imaging

This brief presents a complete set of CMOS basic building blocks for low-cost scanning infrared (IR) cryogenic imagers. Low-power and compact novel circuits are proposed for single-capacitor integration and correlated double sampling, embedded pixel test, pixel charge-multiplexing and video composition and buffering. In order to validate the new basic building blocks, experimental results are reported in standard 0.35-mum CMOS technology for a 50 mum x 100 mum active pixel cell operating at 77 K. Based on the proposed circuits, IR imagers capable of capturing up to 256 x 2560 pixels at 25 fps can be implemented.

Inkjet printed antennas for NFC systems

Inkjet printing is one of the most promising techniques that could potentially revolutionize large area and organic electronics fabrication. At the moment, technology is still under development and some problems remain to be solved. Only few applications have been demonstrated with enough performance to be moved to industrial level. In this paper we present the study of a potentially successful inkjet printing application: a Near Field Communication Antenna. In our work we characterized an inkjet printing process and developed an antenna design to evaluate its potential. Fabricated antenna was tested on NFC systems and final results lead us to conclude that NFC antennas are a potentially successful inkjet printing application.

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

Evaluation of Aerosol, Superfine Inkjet, and Photolithography Printing Techniques for Metallization of Application Specific Printed Electronic Circuits

Application specific printed electronic circuits (ASPECs) are the corresponding term with application-specified ICs for printed electronics. The same as any new technology, printed electronics is suffering from some restrictions in design and process technology aspects. An important stage in the ASPEC design is the final wiring of the organic thin-film transistor arrays or gate arrays to customize it to implement any specific target application that fits in their structure. In this paper, we evaluate two additive manufacturing technologies: aerosol jet using Optomec M3D and electrohydrodynamic printer using superfine inkjet. Both techniques are based on direct-writing of the pattern corresponding to any individual circuit being fabricated (digital printing) enabled by the mask-free noncontact deposition of materials. Finally, these structures will be compared with the corresponding photolithography mask technology. Some parameterized test vehicles, with different instantiations for the variation of line widths and separations, have been designed to be wired using the target technologies. These test vehicles have been fabricated at the Centre for Process Innovation by a five masks lithography and subtractive patterning technology. Results show that both direct printing technologies are feasible for the fabrication of the gate-array customization, thus allowing individual personalization of every circuit what can produce added value functionalities at low cost such as the equivalent effect of having an ROM memory which final contents could be customized at home by using low-cost digital printing technologies. Further interactions between transistor bulk and wiring technologies can improve the obtained performance in order to end up in an industrialized process.

Inkjet Printing Design Rules Formalization and Improvement

A process design kit (PDK) or Technology Design kit (TDK) is a set of files which describes manufacturing parameters that are relevant for the designers (fabrication layers, electrical parameters and design rules) for a certain technology of a given foundry. PDKs customize CAD/EDA tools used by designers, providing enough abstraction of technological details to facilitate the design of (organic electronics) circuits. Design rules are a set of geometric restrictions imposed to the different layers fabricated by the foundry that designers have to respect. By taking the geometric design rules into account, the design engineers address physical layout to develop devices and circuits without the need of a deep knowledge of process and materials. These rules guarantee their manufacturability and enable working circuits with an optimal balance of yield versus integration density. Design rules for inkjet printing are similar to general design rules for photolithographic processes but also need to cope with the failures related to additive printing of inks and related curing. In this paper, parameterizable cells (PCells) have been used to automate the generation of a complete set of structures to formalize and arrive at technology-independent design rules. A set of test vehicles has been designed, printed and characterized demonstrating the methodology to comprehensively capture the design criteria for inkjet printing technology. For improving design rules and scaling down device dimensions, we present a design approach that combines pre-patterned, high-resolution substrates with digital inkjet fabrication as a demonstration of the capabilities of combining inkjet with other fabrication technologies.

A 25-µW All-MOS Potentiostatic Delta-Sigma ADC for Smart Electrochemical Sensors

This paper presents a low-power all-MOS delta-sigma ADC specifically optimized for the potentiostatic biasing and amperometric read-out of electrochemical sensors. The proposed architecture reuses the dynamic properties of the sensor itself to implement a continuous-time mixed electrochemical delta-sigma modulator with minimalist analog circuits fully integrable in purely digital CMOS technologies. A 25-μW smart electrochemical sensor demonstrator integrated in low-cost 1M CMOS technology with Au post-processing is presented. Experimental results show electrical dynamic range values exceeding 10-bit, while electrochemical figures exhibit linearity levels close to R2 = 0.999 combined with RSD <; 15% in terms of reproducibility. A comparative test with commercial potentiostat equipment is also included to qualify the performance of the proposed ADC.

Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits

This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 μm 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.

Development of a standard cell library and ASPEC design flow for Organic Thin Film Transistor technology

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): 1)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.

A 70-

This paper presents a new low-power compact CMOS active pixel circuit specifically optimized for full-field digital mammography. The proposed digital pixel sensor (DPS) architecture includes self-bias capability at ±10% accuracy, up to 15 nA of dark-current autocalibration, built-in test mechanisms, selectable e-/h+ collection, 10-b lossless charge-integration analog-to-digital conversion, more than 1 decade of individual gain tuning for fixed pattern noise cancellation, and a 50-Mb/s digital-only input/output interface. Experimental results for a 70-μm pitch 8-μW DPS cell example are reported in 0.18-μm CMOS 1-polySi 6-metal technology.