Mohammad Mashayekhi

Evaluation of Aerosol, Superfine Inkjet, and Photolithography Printing Techniques for Metallization of Application Specific Printed Electronic Circuits

Application specific printed electronic circuits (ASPECs) are the corresponding term with application-specified ICs for printed electronics. The same as any new technology, printed electronics is suffering from some restrictions in design and process technology aspects. An important stage in the ASPEC design is the final wiring of the organic thin-film transistor arrays or gate arrays to customize it to implement any specific target application that fits in their structure. In this paper, we evaluate two additive manufacturing technologies: aerosol jet using Optomec M3D and electrohydrodynamic printer using superfine inkjet. Both techniques are based on direct-writing of the pattern corresponding to any individual circuit being fabricated (digital printing) enabled by the mask-free noncontact deposition of materials. Finally, these structures will be compared with the corresponding photolithography mask technology. Some parameterized test vehicles, with different instantiations for the variation of line widths and separations, have been designed to be wired using the target technologies. These test vehicles have been fabricated at the Centre for Process Innovation by a five masks lithography and subtractive patterning technology. Results show that both direct printing technologies are feasible for the fabrication of the gate-array customization, thus allowing individual personalization of every circuit what can produce added value functionalities at low cost such as the equivalent effect of having an ROM memory which final contents could be customized at home by using low-cost digital printing technologies. Further interactions between transistor bulk and wiring technologies can improve the obtained performance in order to end up in an industrialized process.

Inkjet Printing Design Rules Formalization and Improvement

A process design kit (PDK) or Technology Design kit (TDK) is a set of files which describes manufacturing parameters that are relevant for the designers (fabrication layers, electrical parameters and design rules) for a certain technology of a given foundry. PDKs customize CAD/EDA tools used by designers, providing enough abstraction of technological details to facilitate the design of (organic electronics) circuits. Design rules are a set of geometric restrictions imposed to the different layers fabricated by the foundry that designers have to respect. By taking the geometric design rules into account, the design engineers address physical layout to develop devices and circuits without the need of a deep knowledge of process and materials. These rules guarantee their manufacturability and enable working circuits with an optimal balance of yield versus integration density. Design rules for inkjet printing are similar to general design rules for photolithographic processes but also need to cope with the failures related to additive printing of inks and related curing. In this paper, parameterizable cells (PCells) have been used to automate the generation of a complete set of structures to formalize and arrive at technology-independent design rules. A set of test vehicles has been designed, printed and characterized demonstrating the methodology to comprehensively capture the design criteria for inkjet printing technology. For improving design rules and scaling down device dimensions, we present a design approach that combines pre-patterned, high-resolution substrates with digital inkjet fabrication as a demonstration of the capabilities of combining inkjet with other fabrication technologies.

Development of a standard cell library and ASPEC design flow for Organic Thin Film Transistor technology

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): 1)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.

Comparison of design styles for top-gate bottom-contact OTFTs

Process yield, variability and scalability have always been a critical issue for scaling-up circuits in printed electronics. The organic materials and fabrication process as well as physical layout design play a significant role in controlling the performance of Organic Thin Film Transistors (OTFT). In order to design a robust and reliable organic circuit, designers are interested in having stable and predictable OTFTs. In this work, we study the electrical characteristics of OTFTs and digital logic cells for different layout design styles, and provide the statistical analysis of their variability and scalability. Arrays of OTFTs and cells have been designed by using parameterized cells (PCells) and python scripts in order to facilitate design parameters sweep. Very high yield and uniform OTFTs have been fabricated with excellent electrical characteristics. Finally some ring oscillator circuits have been demonstrated as a proof of concept.

Inkjet-Configurable Gate Arrays (IGA)

Implementation of organic digital circuits (or printed electronic circuits) has been under an extensive investigation, facing some critical challenges such as process variability, device performance, cell design styles and circuit yield. Failure in any single Organic Thin Film Transistor (OTFT) often causes the whole circuit to fail since integration density is still low. For the same reason, the application of fault tolerant techniques is not that popular in these circuits. In this paper, we propose an approach for the direct mapping of digital functions on top of new prefabricated structures: Inkjet-Configurable Gate Arrays (IGA). This alternative has two main advantages. First, it helps to obtain high yield circuits out of mid-yield foils, and second, it allows implementing individual circuit personalization at a very low cost by using additive mask-less printing techniques thus avoiding the need for OTPROM-like (or E2PROM) devices. All along the design process of IGA cells and structures we used the scalability and technology-independent strategies provided by parameterizable cells (PCell) what helps dealing with current fast technology evolution.

Development of Digital Application Specific Printed Electronics Circuits: From Specification to Final Prototypes

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.

Top-down design flow for application specific printed electronics circuits (ASPECs)

This paper presents a top-down approach for the design process of digital Application Specific Printed Electronics (PE) Circuits (ASPECs); from functionality specification at circuit level (i.e. HDL), through the optimization of combinational circuitry (represented by their logical equations), according to the PMOS-based technology that will be used to build a set of Standard Cells (SC) or use a predesign Inkjet Gate Array (IGA), down to the Place and Route to get the final circuit layout. This process will use the technology coming from the Centre for Process Innovation (CPI). This methodology maps the existing ASIC one by updating design styles and cost functions. Thus, it is portable to different Printed Electronics processes, using state-of-the-art logic synthesis EDA/software tools being the main optimization goal the transistor count. Main reason is that printed electronics technologies show low density and not such high yield compared to traditional Silicon-based microelectronics. To illustrate this methodology, we use the design and implementation of the TicTacToe game to be implemented together with flexible textile pressure sensor and lighting.

Background: Asic Design Methodologies

Integrated Circuit (IC) is a set of electronic devices on a die, made from semiconductor material, normally silicon wafer, each of them holding hundreds of dies. Circuits are built up in many overlapping layers of materials like polysilicon, aluminum, and silicon dioxide, each defined by photolithography. Patterns must be etched into the material to create transistors and interconnections on the surface of the wafer. Etching creates microscopic patterns on the wafer’s surface, and is the true magic of IC technology because it delineates fine geometries using an optical process, forming very small features.

Design-Technology Interaction

Designing devices and circuits demands a basic knowledge of materials, process and interaction among concepts, tools and technologies coming from different engineering disciplines. Designers are responsible for mapping the application requirements, function and performance, into descriptions that can be fabricated using well-established and standardized technological processes. To facilitate manufacturability, the entire fabrication process for any given technology should be controlled by the foundry. Therefore, process and design engineers use standard rules and formats to exchange information while working independently of each others. This set of information for any given technological process is its Process Design Kit (PDK), and is composed of documentation and a set of files related to a given EDA tool customized for the target technology.

Optimization on cell-library design for digital Application Specific Printed Electronics Circuits

This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better designs and fabrication processes, even moving towards integrating logic circuitry together with sensors and actuators. This paper presents considerations for developing (ASPECs), trying to keep a similar approach to the typical ASIC procedures. The work presented herein adopted a cell-based design methodology addressed to printed electronics (PE) designs. Such methodology allows us to propose a design flow for PE similar to the VLSI design flow, comprising logic synthesis, mapping, placement, and routing. In order to evaluate different library compositions, a set of benchmark has been mapped with six different combinations of mapping tools and associated libraries. The obtained results show that a simple library composed of just three cells - either NAND2, NOR2 and inverters or NAND, NAND3 and inverters - performs very well in terms of transistor count. NAND gates are usually preferred options for ratioed PMOS-only design styles. Using a more complex cell library can produce reductions of around 25% in terms of transistor count, but produce increases of around 23% as well.