Jörg Schreiter

An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights

An analog VLSI pulsed neural network for image segmentation using adaptive connection weights is presented. The network marks segments in the image through synchronous firing patterns. The synchronization is achieved through adaption of connection weights. The adaption uses only local signals in a data-driven and self-organizing way. It is shown that for the proposed adaption rules a simple analog VLSI implementation is feasible due to the required local connections and the data-driven self-organizing approach.

High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications

A hardware implementation of an ADPLL-based clock generator is presented. The digital controlled oscillator (DCO) used in the ADPLL generates a clock signal with a high frequency resolution and a small jitter. The presented ADPLL has a fast acquisition and a large pull-in range. The whole design including the DCO has been described in synthesizable VHDL. It does not contain library specific cells, and can be synthesized independently of the standard cell library. Thus, it is portable and the time required to fit it for different semiconductor processes is reduced considerably. The design adaptation cost is limited to adjustment of a few constants in the VHDL-code. The presented design has been implemented in a V400BG432 VIRTEX FPGA and it has been synthesized using two different standard cell libraries (CMOS AMS 0.6 /spl mu/m and CMOS AMS 0.35 /spl mu/m). The maximum achievable clock frequency is 40 MHz using the FPGA and 52 MHz using the above mentioned standard cell libraries. The maximal lock-in time of the ADPLL is 30 reference clock cycles.

Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity

An analog VLSI implementation for pulse coupled neural networks of leakage free integrate-and-fire neurons with adaptive connections is presented. Weight adaptation is based on existing adaptation rules for image segmentation. Although both integrate-and-fire neurons and adaptive weights can be implementation only approximately, simulations have shown, that synchronization properties of the original adaptation rules are preserved.

Simulation and implementation of an analog VLSI pulse-coupled neural network for image segmentation

We present a massively parallel VLSI realization of a pulse-coupled neural network for image segmentation. The network comprises 128 /spl times/ 128 simple nonleaky integrate-and-fire (IAF) neurons with self-organizing inter-neural connections. The prototype implementation also contains analog memories for image storing and a digital readout circuit using an address-event-representation (AER) protocol. The chip has been designed in an Infineon 0.13 /spl mu/m standard CMOS technology.

Minimizing charge injection errors in high-precision, high-speed SC-circuits

In high precision circuits much effort is spent in compensating charge injection effects and usually, the resulting errors are determined by simulation only. However, little attention is paid on a detailed analysis of the charge flow although even simple and basic calculations can provide useful insight. In this paper we consider as example a switched capacitor sample-and-hold-circuit that is frequently used in high-resolution, high-speed analog-to-digital converters. As result of our detailed analysis we obtain analytical expressions that are used to derive rules for increasing the precision of the circuit without reducing its operation speed significantly.

Systematic design of an embedded neural system for automated visual consumption acquisition

Automated consumption meter readout is a subject of commercial interest, because a vast number of installed mechanical meters have to be read manually today. Visual readout by attachment of an embedded system comprising dedicated image sensor, processor, and transmission system as an add-on to existing installed meters is an interesting alternative to the expensive replacement by electronic meters with remote readout. With regard to the underlying large number of potential installation sites, this problem is also an instance of an application where a dedicated implementation can compete with general purpose hardware concerning size and costs. In our approach, we focuses on the compact, cheap, and energy conserving implementation of a neural embedded system for this application. This work also serves as a research vehicle for the long term objective of developing a methodology for systematic and optimized integrated cognitive system design.

An MPSoC for energy-efficient database query processing

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental dataintensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

A New Hierarchical Simulator for Highly Parallel Analog Processor Arrays

System simulation, evaluation and analysis of highly parallel analog systems with conventional simulation tools is quite difficult due to their high complexity. Therefore we developed a methodology for the analysis of such systems by means of an applied simulation system. This approach bases on a relaxation method. The application of this technique accelerates the simulation of highly parallel analog systems by several orders of magnitude compared with standard circuit simulators. As additional feature, it can be traded-off between simulation expenditure and accuracy. We present the simulation method and its advantages in addition to a practical example.

Architektur und Chip-Entwurf des Merkmalserkenners

Wir beginnen mit dem Merkmalserkenner (siehe Kapitel 7), weil er ein einfacheres Netzwerk darstellt als der Merkmalsdetektor (Kapitel 6). Genau genommen beschreiben wir vom Merkmalserkenner nur den inneren Teil und lassen den Synchrondetektor ausen vor. Ferner setzen wir eine spezielle Vernetzung voraus, die nur den ersten Ring von Nachbarn gleichmasig erfasst und der Uberlagerung von einem Merkmalsdetektor mit einem durch 90 Grad- Drehung entstehenden vertikalen Detektor entspricht. Die daraus hervorgehende Rundum-Charakteristik gibt diesem Merkmalserkenner den Namen, namlich Fleckerkenner, und wir setzen ihn fur die Segmentation (siehe Kapitel 5) ein. Bis auf die merkmalsspezifische Vernetzung liegt also ein allgemeiner Merkmalserkenner vor.

Elementare Schaltungen für Neuronen, Synapsen und Photosensoren

Jeder in diesem Buch vorgestellten CMOS-VLSI-Implementierung eines neuronalen Netzwerkes liegt das in Abschnitt 10.3 erlauterte IAF-Neuronmodell zugrunde. Das Membranpotential wird als eine kontinuierliche Zustandsvariable a i beschrieben und ergibt sich aus der Integration der Eingangssignale des Neurons. In der elektronischen Realisierung ist dieses Membranpotential durch einen Spannungswert (Akkumulatorpotential) gegeben, welcher durch die auf der Membrankapazitat gespeicherten Ladung erzeugt wird. Ein mit Hysterese behafteter Schwellwertschalter bestimmt durch Vergleich mit einer Referenzspannung aus dem Akkumulatorpotential die zweiwertige Zustandsvariable x i ∈ {0, 1} des Neurons i. Zum Feuerzeitpunkt nimmt x i den Wert 1 an, der fur die Dauer t d erhalten bleibt, was durch die gezielte Entladung der Kapazitat uber eine Entladestromquelle erreicht wird.