Achim Graupner

Statistical analysis of analog structures through variance calculation

Variance analysis is used for the estimation of how random device parameter variation effects the behavior of analog integrated circuits. This method is very effective if the random parameter deviations can be assumed to be normally distributed and statistically independent and if the nonlinear dependence of the circuit characteristics can be linearized around the nominal (mean) parameter values. It is shown under which conditions the nonlinear dependencies of the system characteristics on the parameters have to be taken into account and how this can improve the accuracy of statistical analysis. This is illustrated with two examples: a transconductance amplifier and an analog filter.

Design and evaluation of current-mode image sensors in CMOS-technology

Three different current-mode-output CMOS image sensor structures comprising of a pixel cell and an appropriate readout circuit have been analyzed and compared with regard to their noise behavior, fixed-pattern noise (FPN), and the dynamic range. First, a standard integrating pixel cell with a readout circuit containing a voltage-to-current converter is proposed. Second, a pixel cell based on a switched current cell is analyzed. The third sensor cell uses a feedback loop to control the reverse bias voltage of the photodiode to reduce the settling time of the pixel cell and the influence of the photodiodess dark current. The necessary amplifier is partly located in the pixel cell and partly in the readout circuit. In all sensors, correlated double sampling is used to suppress the FPN.

CMOS image sensor with shared in-pixel amplifier and calibration facility

A CMOS image sensor is presented which uses a feedback loop to keep the reverse bias voltage of the photo diode on a constant value in order to reduce the dark current. In order to preserve pixel cell area the amplifier required in the feedback loop is located partly in the pixel cell and partly in the readout circuit. The sensor has an on-chip calibration facility, the resulting fixed pattern noise is less than 0.02%. When operated in voltage mode it has a logarithmic response, but it can also be operated in current mode where it shows linear behavior. The proposed pixel cell has been implemented in a 0.6 /spl mu/m CMOS technology. With its size of (15 /spl times/ 15)/spl mu/m/sup 2/ it is only slightly larger than a standard integrating pixel cell with approximately the same photosensitivity while having approximately the same power dissipation. The fill factor is about 27%. The pixel cell is suited for video rate operation (50 fps) in image sensor arrays with moderate resolution.

Minimizing charge injection errors in high-precision, high-speed SC-circuits

In high precision circuits much effort is spent in compensating charge injection effects and usually, the resulting errors are determined by simulation only. However, little attention is paid on a detailed analysis of the charge flow although even simple and basic calculations can provide useful insight. In this paper we consider as example a switched capacitor sample-and-hold-circuit that is frequently used in high-resolution, high-speed analog-to-digital converters. As result of our detailed analysis we obtain analytical expressions that are used to derive rules for increasing the precision of the circuit without reducing its operation speed significantly.

A New Hierarchical Simulator for Highly Parallel Analog Processor Arrays

System simulation, evaluation and analysis of highly parallel analog systems with conventional simulation tools is quite difficult due to their high complexity. Therefore we developed a methodology for the analysis of such systems by means of an applied simulation system. This approach bases on a relaxation method. The application of this technique accelerates the simulation of highly parallel analog systems by several orders of magnitude compared with standard circuit simulators. As additional feature, it can be traded-off between simulation expenditure and accuracy. We present the simulation method and its advantages in addition to a practical example.

Statistical Analysis of Analogue Structures

This paper treats the tolerance analysis of analogue systems with the objective of statistical modelling of complex analogue systems. A methodology using variance calculation is proposed and compared with Monte-Carlo simulation in terms of effort and accuracy. It is shown that for variance calculation a linear approxiation is sufficient for typical analog circuits and that it requires less effort than Monte-Carlo analysis while providing comparable or even better accuracy.

A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing

We present a system-on-chip realization of a CMOS image sensor with on-chip block transformation or spatial convolution capabilities and digital output. The necessary operations are realized with analog current-mode circuits. The digital kernel-coefficients for transformations or convolutions can be set arbitrarily. The prototype implementation is comprised of a 128/spl times/64 pixel CMOS image sensor, signal conditioning, a low-power mixed-signal multiplier array and a dedicated multi-input pipelined A/D converter. The design is scalable up to high sensor resolutions. The prototype was implemented in a standard 0.6 /spl mu/m, double metal, double poly CMOS technology and dissipates 100 mW at 5 V power supply.

Design of parallel preprocessing image sensors

In this paper we propose an architecture for an image sensor with an embedded low-power analog preprocessing unit dedicated for convolution-type filtering. The convolution of the analog image data with the digital convolution kernel is realized using a sequential bit-wise principle. For the subsequent bit-shifted addition a modified current-mode pipelined A/D converter is suggested.