Jorge Portilla

Embedded Runtime Reconfigurable Nodes for Wireless Sensor Networks Applications

The use of reconfigurable hardware (HW) can improve the processing performance of many systems, including Wireless Sensor Networks (WSNs). Moreover, reconfigurable devices permit remote and runtime HW reconfiguration, which implies benefits in WSNs deployment and maintainability and, finally, cost reduction. In this paper, WSN node runtime reconfigurability is tackled from several aspects. First, the sensor node includes a commercial reconfigurable device, a Field Programmable Gate Array (FPGA), that permits to take advantage of the tools and support provided by the industry, while exploiting the inherent hardware parallelism. Second, two software (SW) and hardware reconfiguration scenarios are defined along with a support middleware. Third, in order to provide runtime reconfigurability to the WSN node, a complete runtime reconfigurable system has been defined and designed for the FPGA included in the node. Fourth, the HW reconfiguration cost has been evaluated, as well as the cost of transmitting new HW configurations and SW programs through the network, based on a set of defined parameters. Finally, the feasibility of the runtime reconfigurable system has been demonstrated with a use case.

A Reconfigurable Fpga-Based Architecture for Modular Nodes in Wireless Sensor Networks

A reconfigurable platform for sensor networks is presented. This platform has features that allow easy reuse of the node in several applications avoiding redesigning the system from scratch. The node includes an FPGA which is the core of the reconfiguration capabilities of the node. Several hardware interfaces for sensor standard protocols like I2C or PWM have been developed and implemented in the FPGA. Remote reconfiguration is an important feature and sensor networks can take advantage of it in order to improve the global performance.

Remote HW-SW reconfigurable Wireless Sensor nodes

Reconfigurable HW, like FPGAs, can improve the processing systems performance as it has been demonstrated by several research groups. Usually, the inclusion of such elements in HW platforms for Wireless Sensor Networks (WSNs) has been rejected by designers, mainly due to the power consumption penalization. A reconfigurable device allows not only performance improvement but also remote HW reconfiguration of the WSN node. In this paper, a entire working flow for generate, remotely configure and reconfigure the HW in a target custom reconfigurable platform developed at CEI (Centro de Electronica Industrial) is presented. The custom platform includes a microprocessor and an FPGA (Xilinx partially reconfigurable) to carry out all the processing tasks. The current reconfiguration process works with the JTAG interface, which makes the solution portable to other FPGAs, especially those new less power consuming devices that are appearing in the market nowadays.

Power management techniques in an FPGA-based WSN node for high performance applications

In this work, the power management techniques implemented in a high-performance node for Wireless Sensor Networks (WSN) based on a RAM-based FPGA are presented. This new node custom architecture is intended for high-end WSN applications that include complex sensor management like video cameras, high compute demanding tasks such as image encoding or robust encryption, and/or higher data bandwidth needs. In the case of these complex processing tasks, yet maintaining low power design requirements, it can be shown that the combination of different techniques such as extensive HW algorithm mapping, smart management of power islands to selectively switch on and off components, smart and low-energy partial reconfiguration, an adequate set of save energy modes and wake up options, all combined, may yield energy results that may compete and improve energy usage of typical low power microcontrollers used in many WSN node architectures. Actually, results show that higher complexity tasks are in favor of HW based platforms, while the flexibility achieved by dynamic and partial reconfiguration techniques could be comparable to SW based solutions.

Integrated hardware interfaces for modular sensor networks

Sensor networks have reached a great relevance during the last years. The idea is to use a large number of nodes measuring different physical parameters in several environments, which implies different research challenges (low power consumption, communication protocols, platform hardware design, etc). There is a tendency to use modular hardware nodes in order to make easier rapid prototyping as well as to be able to redesign faster and reuse part of the hardware modules. One of the main obstacles for rapid prototyping is that sensors present heterogeneous interfaces. In this paper, a VHDL library for sensors/actuators interfaces is proposed. The purpose is to have a set of different sensor interfaces that include the most common in the sensors/actuators world, enabling the rapid connection to a new sensor/actuator. Moreover, the concept presented here may be used for new interfaces that can be easily developed. The VHDL implementation is independent of the final platform (any FPGA or ASIC) in order to minimize redesign effort and make easier rapid prototyping. The interfaces are installed in a UPM platform for sensor networks.

High speed Radix-4 soft-decision Viterbi decoder for MB-OFDM UWB system

In this paper, a 64 state soft decision Viterbi Decoder (VD) system by using a high speed radix-4 Add Compare Select (ACS) architecture is presented. The proposed VD system can support different data rate (from 53.5 Mbps to 480 Mbps) for Multiband Orthogonal Frequency-division Multiplexing (MB-OFDM) Ultra-Wideband (UWB) system when implemented onto the FPGA board. The proposed VD employs efficient two steps Radix 4 architecture, which is responsible of calculating two steps of 64 state Radix 4 Branch Metrics (BM) within one clock cycle. The branch metrics are calculated using a uniform distance measurement algorithm, which equals to the symbol itself when compared to logic-0 and equal to its one’s complement when compared to logic-1. By employing the modified Modulo Normalization algorithm, it is possible to use only a 10- bit memory block to restore each of the 64 state metrics, with the advantage of avoiding errors caused by overflow during the updating process for state metrics, and simplifying the comparator circuit of the ACS unit. The Two Pointer Even Algorithm, which is considered to be very simple and more hardware-efficient than the register exchange algorithm, is used for tracing back the survivor sequence and output the decoded data stream. 3-bit soft decision input sequences are used for gathering the experimental results. The sampling frequency of the MBOFDM UWB system is 528 MHz, by using the proposed two steps Radix 4 VD architecture we can process 4 input signals in parallel within one clock cycle, therefore only 132 MHz operating frequency is needed for the proposed VD system. This will dramatically reduce the dynamic power consumption for hardware implementation. Final results of the implementation show that the proposed VD architecture can support a maximum working frequency of 152.5 MHz on Xilinx XUPV5-LX110T Evaluation Platform.

Hardening digital systems with distributed functionality: robust networks

Collaborative hardening and hardware redundancy are nowadays the most interesting solutions in terms of fault tolerance achieved and low extra cost imposed to the project budget. Thanks to the powerful and cheap digital devices that are available in the market, extra processing capabilities can be used for redundant tasks, not only in early data processing (sensed data) but also in routing and interfacing1