Yana Esteves Krasteva

Embedded Runtime Reconfigurable Nodes for Wireless Sensor Networks Applications

The use of reconfigurable hardware (HW) can improve the processing performance of many systems, including Wireless Sensor Networks (WSNs). Moreover, reconfigurable devices permit remote and runtime HW reconfiguration, which implies benefits in WSNs deployment and maintainability and, finally, cost reduction. In this paper, WSN node runtime reconfigurability is tackled from several aspects. First, the sensor node includes a commercial reconfigurable device, a Field Programmable Gate Array (FPGA), that permits to take advantage of the tools and support provided by the industry, while exploiting the inherent hardware parallelism. Second, two software (SW) and hardware reconfiguration scenarios are defined along with a support middleware. Third, in order to provide runtime reconfigurability to the WSN node, a complete runtime reconfigurable system has been defined and designed for the FPGA included in the node. Fourth, the HW reconfiguration cost has been evaluated, as well as the cost of transmitting new HW configurations and SW programs through the network, based on a set of defined parameters. Finally, the feasibility of the runtime reconfigurable system has been demonstrated with a use case.

A Fast Emulation-Based NoC Prototyping Framework

This paper presents an FPGA emulation-based fast network on chip (NoC) prototyping framework, called dynamic reconfigurable NoC (DRNoC) emulation platform. The main, distinguishing, characteristic of this approach is that design exploration does not requires re-synthesis, accelerating the process. For this aim, partial reconfiguration capabilities of some state of the art FPGAs have been developed and applied. The paper describes all the building elements of the proposed solution: the used partial reconfiguration approach, the design space exploration framework itself, and the data measuring system. Results and a use case are shown.

Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs

Virtex II FPGAs are widely used in current designs because of their high density of logic cells and the availability of embedded DSP specific blocks (Multipliers) and Dual port RAMs along with the possibility of dynamic reconfiguration. Systems containing FPGAs could be updated once deployed by loading new configurations received, i.e., via a network connection. Unlike other approaches, which rely on more regular devices, i.e. the older Virtex FPGAs, this paper presents a solution for dynamic core insertion and reallocation that permits cores to make use of the embedded blocks available in Virtex II devices. An application called BITPOS is proposed. It extracts and reallocates Virtex II cores. It is compared with other similar solutions and a survey of existing core generation tools is presented. A feasible slot based architecture with a bus communication structure for reallocatable cores communication has been selected and applied in a prototype demonstrator.

Remote HW-SW reconfigurable Wireless Sensor nodes

Reconfigurable HW, like FPGAs, can improve the processing systems performance as it has been demonstrated by several research groups. Usually, the inclusion of such elements in HW platforms for Wireless Sensor Networks (WSNs) has been rejected by designers, mainly due to the power consumption penalization. A reconfigurable device allows not only performance improvement but also remote HW reconfiguration of the WSN node. In this paper, a entire working flow for generate, remotely configure and reconfigure the HW in a target custom reconfigurable platform developed at CEI (Centro de Electronica Industrial) is presented. The custom platform includes a microprocessor and an FPGA (Xilinx partially reconfigurable) to carry out all the processing tasks. The current reconfiguration process works with the JTAG interface, which makes the solution portable to other FPGAs, especially those new less power consuming devices that are appearing in the market nowadays.

Wireless sensor network modular node modeling and simulation with VisualSense

Wireless sensor networks (WSNs) have been studied deeply during the last years, but real deployments with thousands of motes are really critical in cost, time and reliability due to several problems: commissioning, debugging, etc. In this context, simulation is becoming mandatory to reduce the potential failures of the WSN before deployment, which is very costly. In this paper, a simulation approach for WSNs nodes is presented, based in the Ptolemy simulation environment, specifically in VisualSense. The simulation is carried out over specific hardware, a modular platform for WSNs, whose main feature is the modularity. Therefore, the simulation is also modular, making the process very flexible to modifications of the HW to be simulated and to the operation conditions.

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs. Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration. The paper includes a brief description of all the building elements of the emulation framework and a use case that demonstrates the advantages of the designed pRTRs.

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements of hardware IPs, functional scalability has been identified as an interesting feature. The proposal in this paper is to take advantage of the regularity and the high-processing capability of systolic arrays, to develop run-time functional scalable cores, making use of spatial scalability, by means of replicating and relocating basic processing elements of the array. The relocation process is performed using the dynamic-reconfiguration possibilities offered by commercial FPGAs. In this paper, an architectural template is proposed to develop systolic scalable coprocessors following this approach, together with its corresponding software drivers that may be executed within an embedded processor. In addition, a design flow is proposed to adapt the architectural template to different problems, together with some examples of scalable cores created following this design. This solution provides better results, regarding the reconfiguration time and the memory necessity overhead, compared with other dynamically scalable solutions.

Generic systolic array for run-time scalable cores

This paper presents a scalable core architecture based on a generic systolic array. The size of this kind of cores can be adapted in real-time to cover changing application requirements or to the available area in a reconfigurable device. In this paper, the process of scaling the core is performed by the replication of a single processing element using run-time partial reconfiguration. Furthermore, rather than restricting the proposed solution to a given application, it is based on a generic systolic architecture which is adapted using a design flow which is also proposed. The paper includes a related work discussion, the proposal and definition of a systolic array communication approach, which does not require the use of specific macro structures and permits to achieve higher flexibility, and a design flow used to adapt the generic architecture. Further, the paper also includes an image filter application as a simple use case, along with implementation results for Virtex 5 FPGA.

Wireless Sensor Networks: From Real World to System Integration – Alternative Hardware Approaches

The way in which measures from environment are taken has changed. In the past, different sensors close to the point of interest were placed and wired to a central station where the processing was carried out. Currently, the new paradigm of massive measurement is represented by wireless sensor networks. In this new scenario, distributed tiny nodes measure parameters and send the information wirelessly and even process data locally, performing distributed computing in the network. These nodes are autonomous and nonintrusive.

Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management

In this paper we present an FPGA partition architecture, a methodology and a set of supporting tools that enable the use of partial reconfiguration in two directions: the (re)allocation of tasks within a slot based FPGA arrangement, and the reconfiguration of the communication infrastructure between these tasks and with an external processor. Thus, embedded reconfigurable devices can operate autonomously to adapt themselves when they receive a new task or group of tasks, optimizing both task allocation and intra-task communications. The type of communication structures supported can be a combination of buses, point-to point connections and networks-on-chip (NoC), each with variable width, sharing a fixed set of intra-task communication channels. Results are shown for a remote reconfiguration application, and additional experiments for reconfigurable NoCs are also shown.