Joris Peeters

Thermomechanical models for leadless solder interconnections in flip chip assemblies

Analytical thermomechanical models have been developed in order to calculate the thermally induced stresses in leadless solder interconnection systems. Two different analytical models are highlighted: the peripheral and area array thermomechanical model which describe the thermally induced stresses for two components connected to each other with a peripheral, respectively, area array of joints. The analytical models are based on structural mechanics and have the ability to characterize the nature and estimate the magnitude of the joint stresses. Using these models, structural design optimization of interconnection systems can be performed very quickly in order to reduce time consuming experiments and finite element simulations. It is found that the largest stresses in the solder joints of flip chip assemblies are at the top and bottom surface of the connection and that they are especially caused by bending moments subjected to the joints. Comparisons with finite element simulations have proved a good accuracy of the thermomechanical models.

Broadband modeling and transient analysis of MCM interconnections

In this paper, conductive losses of multi-chip module interconnections are analysed. A distributed network model for the conductor surface impedance is extended to include the transition from DC resistivity to high frequency losses and to cover the effect of barrier and adhesion layers. Using this model, a broadband loss expression is derived. This loss expression can be implemented in network simulators for transient analysis of lossy interconnections. The validity and applicability of the model is experimentally verified by comparison with measured S-parameters. Measurements extend from 45 MHz to 18 GHz. They are performed on test structures realised with two different MCM-D technologies. Excellent correspondence between measurements and simulations is achieved, even when magnetic effects of a thick nickel barrier layer are involved. The models are incorporated in the transient analysis network simulation program Transplus. Several simulation examples using Transplus are shown. >

Signal propagation in high-speed MCM circuits

This paper describes the analysis of the propagation of digital signal on a thin-film multichip module (MCM) substrate populated with CMOS integrated circuits. Timing analyses and circuit simulations were performed during the design of an MCM consisting of 4 bare 0.7-/spl mu/m CMOS ASICs (100 pins, 64 mm/sup 2/, standard cell technology) transmitting signals at 200 Mbit/s on a 5-layer thin-film substrate (1-by-1 inch, 2 interconnection layers). This paper addresses mainly two problems related to the design of microsystems where trade-offs must be found between high frequency and high density requirements: 1) an accurate description of the chip-to-chip, propagation of the signals, including the combined influence of active devices (drivers and receivers) and coupled, lossy interconnection lines: 2) an accurate overview of the way parameters from different domains (geometrical, electrical and technological) interact with each other and affect together the signal propagation. It is shown how the results of such analyses can help solving trade-offs between different requirements and taking decisions during the system design phase.

A broad band loss model for MCM interconnections

Conductive losses of multichip module interconnections are analyzed. A distributed network model for the conductor surface impedance is extended to include transition to DC resistivity and the effect of barrier and adhesion layers. Using the model, a broadband loss expression suitable for use in fast Fourier transform (FFT)-based transient analysis network simulators for digital signal transmission on lossy interconnections is derived. The expression is used to model measured scattering parameter characteristics up to 18 GHz, for different line types. Excellent correspondence between measurements and simulations is achieved, even when magnetic effects of a thick nickel barrier layer are involved. Finally, the models are incorporated in a transient analysis network simulation program.<<ETX>>

Rated Life Calculation Potential of Gearbox Model Based Force Estimates

One main contributor for gearbox rated lifetime estimation is the assessment of bearing loading during predicted operating conditions. This paper investigates an approach to determine input bearing loading by means of a TPA (Transfer Path Analysis) approach. TPA is suggested to retrieve internal bearing forces from acceleration measurements acquired at the outside of the gearbox housing. However, classical TPA methods would require the gearbox to be dismantled during the transfer path determination process. This poses significant practical challenges. To overcome this issue, this paper investigates the possibility of using a flexible multibody simulation model to calculate the different frequency response functions between bearings forces and acceleration sensors. All simulations use a flexible multibody modeling approach, which has been extensively validated. Main results of this validation process have been published by the authors in the past. The paper discusses the results of such analysis on a multi-megawatt wind turbine gearbox. Here, simulated acceleration measurements on the gearbox housing are processed into bearing forces. The feasibility of using these forces for a rating life calculation is investigated.

Interconnect technologies for multi-chip modules: high frequency characterization and loss analysis

A thin film interconnect technology was characterised up to 18 GHz. The focus was put on the analyses of conductive losses. An equivalent model for the conductor internal impedance was extended to include low frequency loss behaviour and the effect of a metal barrier. A good correspondence with the measurements was achieved.

A Resonant Tunneling High Electron Mobility Transistor

A double barrier resonant tunneling heterostructure has been combined with a pseudomorphic high electron mobility transistor. This three terminal device shows negative transconductance in addition to a clear negative differential resistance region which shifts with gate voltage. The device characteristics can be adequately explained by a simple device simulation model. Flip-flop and frequency doubling operations at room temperature are demonstrated.