Luis M. Flores-Nava

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

FGPA development and implementation of a solar panel emulator

This work describes the development and FPGA implementation of a solar panel emulator. First we created the electric analog model of the solar panel using the Mentor Graphics framework, using the irradiance and temperature variables of a meteorological database as input signals and then obtaining the short circuit current and the open circuit voltage parameters to finally train an artificial neural network using Matlab, to perform the modeling of the response of the solar panel. Once the neural network was optimized, this was described in VHDL to simulate its response, to finally make its implementation in FPGA digital device and to be able to compare these results with those of a commercial solar panel.

Multilayer perceptron network with integrated training algorithm in FPGA

In this manuscript we present the implementation of an artificial neural network type Multilayer Perceptron (ANN-MP or NNMP) in Field-Programmable Gate Arrays (FPGA), including Back-Propagation training method based on descendent gradient. This network has 2 reconfigurable hidden layers, adjustable parameters (epochs and ratio learning) and batch learning. The proposed architecture aims to reduce the number of logical elements to be used, so serial processing is utilized. In order to test the performance of the trained network, a nonlinear function was approximated with satisfactory results.

Photovoltaic panel emulator in FPGA technology using ANFIS approach

In this manuscript we present the implementation in FPGA of ANFIS system (Adaptive Network-based Fuzzy Inference Systems) for a two-input architecture with three membership functions per input and nine fuzzy rules, used to set up a photovoltaic panel emulator. The starting point is the photovoltaic panel electric analog model simulated with ELDO, a tool of Mentor Graphics Suite, having as inputs irradiation and temperature from a meteorological data base so we can obtain the short-circuit current (Isc) and open circuit voltage (Voc) of the panel. With this information, ANFIS was trained within Matlab environment to approximate the photovoltaic panel response. The training was carried out for both, current and voltage, independently, and once achieved minimum error parameters, they were downloaded into the FPGA implemented architecture in order to assess its performance.

CMOS analog neurofuzzy prototype based on ANFIS

The architecture called ANFIS (Adaptive Neuro-Fuzzy Inference System) proposed by J.R. Jang (1993) is divided in five layers. Layers 1 and 2 in ANFIS were built by using a double-differential amplifier and a winner takes all circuit; to implement layers 3, 4 and 5, CMOS translinear blocks are used. The complete ANFIS architecture is implemented on a circuit board, using two CMOS circuits (N-well and 2 /spl mu/m minimum dimensions). The total system has two inputs with three membership functions each one, which generate a fuzzy space with nine subspaces and one single output. The system is used for classification of electrical signals.

DSP Implementation of Extended Infomax ICA Algorithm for Blind Source Separation

In this paper we use a digital signal processing unit (DSP) to implement an extended Infomax independent component analysis (ICA) algorithm for blind source separation (BSS). In this work we are going to reproduce the performance of the net implementation as expected in Matlab. A first hardware implementation has been designed and the experimental results are presented. In the developed experiments we used recorded signals and then they were processed in the DSP unit in real-time. The performance comparison are made with 2times2 net

3-layered capacitive structure design for MEMS inertial sensing

In this paper a two-terminal capacitive structure is presented in which a novel architecture with a double interleaved (interdigitated) scheme is introduced. This structure was originally conceived as a mechanism to achieve a greater capacitance between the plates (terminals) of an integrated capacitor using a relatively smaller design area in the standard 0.5μm, two polysilicon and three metal layers (2P3M) CMOS technology. This work presents the design and theoretical analysis of a three-metal interleaved structure used as a varactor tied down to the proof mass of an integrated CMOS-MEMS accelerometer where the active devices are floating-gate transistors (FGMOS) with a variable capacitive coupling coefficient. Nevertheless, the three-layered geometrical scheme may have a wide range of applications across the MEMS technology.

Model for a CMOS Bit-Level Product Cell

An analysis method for a bit-level product cell used for vector-matrix multiplications is presented. The cell is a combination of a charge injection binary multiplier and an analog accumulator. CID/CCD principles help to understand the cell function and MOS structure equations are used to describe the cell operations.

CMOS cells with continuously adjustable parameters for implementation of fuzzy and neurofuzzy systems

The use of fuzzy logic, neural networks, and more recently, neurofuzzy systems, has increased the necessity of counting with efficient architectures to solve the problems present in many research areas, not only at software level, but at hardware level, which presents a higher performance in most applications. In this manuscript we present a novel set of basic analog CMOS cells to generate triangular membership functions, which can adjust continuously their parameters in current-mode. This characteristic results crucial when implementing neurofuzzy systems such as NEFCLASS, NEFPROX and NEFCON architectures, which are aimed at in this work, nevertheless our cells will work well in any fuzzy/neuro fuzzy system using triangular, left and right shoulder membership functions. The proposed cells are extensions of those originally presented in early research, in such a way that the current gain can be electrically modified and set to the optimal value required by the neurofuzzy system.

Motion detection sensor based on CMOS floating-gate devices

This work presents a novel motion-detection sensor, based on CMOS technology. It uses floating-gate transistors to perform signal aggregation computation, as part of the centroid approximation, for 1-D real-time tracking of a regular-shape object. In fact, the object is detected from binary images, which are captured within the field of view of this sensor. The analog-weighting process for the spatial column-components, in the associated algorithm, is realized by using MOS transistors operating in the triode region. Only binary images are considered, even though image information is sacrificed, faster operation speed and increased functionality is obtained. The motion-detection sensor was fabricated using a 1.2μm, n-well, CMOS process. The design contains a 17x18 cell-array with a fill-factor is 35.6%. The electrical analysis supported by PSpice of this initial CMOS integrated circuit, demonstrates that its extension to a larger prototype for robotic applications is attractive.