Jose Angel Ortiz Gonzalez
University of Warwick
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Featured researches published by Jose Angel Ortiz Gonzalez.
IEEE Transactions on Industrial Electronics | 2016
Saeed Jahdi; Olayiwola M. Alatise; Jose Angel Ortiz Gonzalez; Roozbeh Bonyadi; Li Ran; Philip A. Mawby
The temperature and dV/dt dependence of crosstalk has been analyzed for Si-IGBT and SiC-MOSFET power modules. Due to a smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot-through currents compared with similarly rated Si-IGBT modules in spite of switching with a higher dV/dt and with a lower threshold voltage. However, due to high voltage overshoots and ringing from the SiC Schottky diode, SiC modules exhibit higher shoot-through energy density and induce voltage oscillations in the dc link. Measurements show that the shoot-through current exhibits a positive temperature coefficient for both technologies, the magnitude of which is higher for the Si-IGBT, i.e., the shoot-through current and energy show better temperature stability in the SiC power module. The effectiveness of common techniques of mitigating shoot-through, including bipolar gate drives, multiple gate resistance switching paths, and external gate-source and snubber capacitors, has been evaluated for both technologies at different temperatures and switching rates. The results show that solutions are less effective for SiC-MOSFETs because of lower threshold voltages and smaller margins for negative gate bias on the SiC-MOSFET gate. Models for evaluating the parasitic voltage have also been developed for diagnostic and predictive purposes. These results are important for converter designers seeking to use SiC technology.
IEEE Transactions on Power Electronics | 2015
Saeed Jahdi; Olayiwola M. Alatise; Roozbeh Bonyadi; Petros Alexakis; Craig A. Fisher; Jose Angel Ortiz Gonzalez; Li Ran; Philip A. Mawby
The tradeoff between the switching energy and electro-thermal robustness is explored for 1.2-kV SiC MOSFET, silicon power MOSFET, and 900-V CoolMOS body diodes at different temperatures. The maximum forward current for dynamic avalanche breakdown is decreased with increasing supply voltage and temperature for all technologies. The CoolMOS exhibited the largest latch-up current followed by the SiC MOSFET and silicon power MOSFET; however, when expressed as current density, the SiC MOSFET comes first followed by the CoolMOS and silicon power MOSFET. For the CoolMOS, the alternating p and n pillars of the superjunctions in the drift region suppress BJT latch-up during reverse recovery by minimizing lateral currents and providing low-resistance paths for carriers. Hence, the temperature dependence of the latch-up current for CoolMOS was the lowest. The switching energy of the CoolMOS body diode is the largest because of its superjunction architecture which means the drift region have higher doping, hence more reverse charge. In spite of having a higher thermal resistance, the SiC MOSFET has approximately the same latch-up current while exhibiting the lowest switching energy because of the least reverse charge. The silicon power MOSFET exhibits intermediate performance on switching energy with lowest dynamic latching current.
IEEE Transactions on Power Electronics | 2015
Roozbeh Bonyadi; Olayiwola M. Alatise; Saeed Jahdi; Ji Hu; Jose Angel Ortiz Gonzalez; Li Ran; Philip A. Mawby
In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs.
IEEE Transactions on Power Electronics | 2016
Ji Hu; Olayiwola M. Alatise; Jose Angel Ortiz Gonzalez; Roozbeh Bonyadi; Li Ran; Philip A. Mawby
Nonuniformities in the electrothermal characteristics of parallel connected devices reduce overall reliability since power is not equally dissipated between the devices. Furthermore, a nonuniform rate of operational degradation induces electrothermal variations thereby accelerating the development of failure. This paper uses simulations and experiments to quantitatively and qualitatively investigate the impact of electrothermal variations on the reliability of parallel connected power devices under unclamped inductive switching (UIS) conditions. This is especially pertinent to SiC where small die areas mean devices are often connected in parallel for higher current capability. Measurements and simulations show that increasing the variation in the initial junction temperatures and switching rates between parallel connected devices under UIS reduces the total sustainable avalanche current by 10%. It is seen that the device with the lower junction temperature and lower switching rate fails. The measurements also show that the maximum sustainable avalanche energy for a given variation in junction temperature and switching rate increases with the avalanche duration, meaning that the effect of electrothermal variation is more critical with high power (high current and low inductor) UIS pulses compared with high energy (low current and high inductance) pulses. These results are important for condition monitoring and reliability analysis.
IEEE Transactions on Industrial Electronics | 2016
Ji Hu; Olawiwola Alatise; Jose Angel Ortiz Gonzalez; Roozbeh Bonyadi; Petros Alexakis; Li Ran; Philip A. Mawby
Differences in the thermal and electrical switching time constants between parallel-connected devices cause imbalances in the power and temperature distribution, thereby reducing module robustness. In this paper, the impact of electrothermal variations (gate and thermal resistance) between parallel-connected devices on module robustness is investigated for 900-V-CoolMOS and 1.2-kV-SiC MOSFETs under clamped inductive switching (CIS) and unclamped inductive switching (UIS). Under CIS, the difference in the steady-state junction temperature (ΔTJ) and switching energy (ΔESW) between the parallel-connected devices for a given difference in the gate and thermal resistance (ΔRG and ΔRTH) is used as the metric for determining robustness to electrothermal variations, i.e., how well the devices maintain uniform temperature inspite of switching with different rates and thermal resistances. Under UIS conditions, the change in the maximum avalanche current/energy prior to device failure as a function of the ΔTJ and ΔRG between the parallel-connected devices is used as the metric. Under both CIS and UIS, SiC devices show better performance with minimal negative response to electrothermal variations between the parallel-connected devices. Finite-element models have also been performed showing the dynamics of BJT latch-up during UIS for different technologies.
IEEE Transactions on Device and Materials Reliability | 2017
Borong Hu; Jose Angel Ortiz Gonzalez; Li Ran; Hai Ren; Zheng Zeng; Wei Lai; Bing Gao; Olayiwola M. Alatise; Hua Lu; C. Bailey; Philip A. Mawby
The superior electro-thermal properties of silicon carbide (SiC) power devices permit higher temperature of operation and enable higher power density compared with silicon devices. Nevertheless, the reliability of SiC power modules has been identified as a major area of uncertainty in applications which require high reliability. Traditional power module packaging methods developed for silicon chips have been adopted for SiC and the different thermomechanical properties cause different fatigue stresses on the solder layer of the chip. In this paper, a 2-D finite element model has been developed to evaluate the stress performance and lifetime of the solder layer for Si devices, which has been validated using accelerated power cycling tests on Si IGBTs. The proposed model was extrapolated for SiC devices of the same voltage and current rating using the same solder material and the results show that under the same cyclic power loss profile the induced stress and strain energy in the die attach layer is much higher and concentrates on the die/solder interfacial area for SiC chips. Using the validated stress-based model, the lifetime can be quantified when SiC chips are used. This ability to extrapolate the available power cycling and lifetime data of silicon chips to SiC chips would be a key element for developing reliable packaging methods for SiC devices.
european conference on cognitive ergonomics | 2016
Jose Angel Ortiz Gonzalez; Olayiwola M. Alatise; Li Ran; Philip A. Mawby; Pushparajah Rajaguru; C. Bailey
Fast switching SiC Schottky diodes are known to exhibit significant output oscillations and electromagnetic emissions in the presence of parasitic inductance from the package/module connections. Furthermore, solder pad delamination and wirebond lift-off are common failure modes in high temperature applications. To this end, pressure packages, which obviate the need for wire-bonds and solder/die attach, have been developed for high power applications where reliability is critical like thyristor valves in HVDC line commutated converters. In this paper, SiC Schottky diodes in pressure-packages (press-pack) have been designed, developed and tested. The electrothermal properties of the SiC diode in press-pack have been tested as a function of the clamping force using different thermal contacts, namely molybdenum and Aluminum Graphite. Finite Element Simulations have been used to support the analysis.
european conference on cognitive ergonomics | 2015
Saeed Jahdi; Olayiwola M. Alatise; Jose Angel Ortiz Gonzalez; Li Ran; Philip A. Mawby
The temperature and dV/dt dependence of false turn-ON has been analyzed for Silicon Carbide (SiC) Unipolar and Silicon Bipolar transistors, with switching rates varied by the gate resistances while temperature is varied by a hot plate connected to power modules. Self-heating is also investigated by measuring the temperature rise of the modules at high switching frequencies (8 kHz). This has resulted in continuous false turn-on occurrence in the device which has increased the device junction temperature significantly due to the repetitive shoot-through energy. Temperature rises of up to 150°C within just a few minutes have been observed as a result of repetitive shoot-through currents at high frequencies. To understand the impact of different mitigation techniques, the temperature rise is also observed after applying the corrections. It is seen that using the correction methods in the devices reduces the temperature rise significantly and therefore is vital for the applications of both Silicon and SiC devices.
international symposium on power semiconductor devices and ic's | 2017
Jose Angel Ortiz Gonzalez; Olayiwola M. Alatise; Philip A. Mawby; Attahir Murtala Aliyu; Alberto Castellazzi
Pressure contact packages have demonstrated an improved reliability for silicon devices due to the elimination of the weak elements of the packaging, namely wirebonds and solder. This packaging approach has not yet been widely studied for SiC devices, however, it is of high interest for applications like HVDC or rail traction, where the wide bandgap properties of SiC devices can be fully exploited and high reliability is critical. Current IGBT press-pack modules use Si PIN diodes for enabling reverse conduction, however, the use of SiC Schottky diodes would be beneficial given their better characteristics including low switching losses and lower zero temperature coefficient (ZTC) for electrothermal stability of diodes in parallel. A prototype for the evaluation of SiC Schottky diodes using pressure contacts has been designed, built and tested for both single die and multiple die.
IEEE Transactions on Industrial Electronics | 2017
Jose Angel Ortiz Gonzalez; Olayiwola M. Alatise; Attahir Murtala Aliyu; Pushparajah Rajaguru; Alberto Castellazzi; Li Ran; Philip A. Mawby; C. Bailey
The thermomechanical reliability of SiC power devices and modules is increasingly becoming of interest especially for high-power applications, where power cycling performance is critical. Press-pack assemblies are a trusted and reliable packaging solution that has traditionally been used for high-power thyristor-based applications in FACTS/HVDC, although press-pack IGBTs have become commercially available more recently. These press-pack IGBTs require antiparallel PiN diodes for enabling reverse conduction capability. In these high-power applications, paralleling chips for high current conduction capability is a requirement, hence, electrothermal stability during current sharing is critical. SiC Schottky diodes not only exhibit the advantages of wide bandgap technology compared to silicon PiN diodes, but they have significantly lower zero temperature coefficient (ZTC), meaning they are more electrothermally stable. The lower ZTC is due to the unipolar nature of SiC Schottky diodes as opposed to the bipolar nature of PiN diodes. This paper investigates the implementation and reliability of SiC Schottky diodes in press-pack assemblies. The impact of pressure loss on the electrothermal stability of parallel devices is investigated.