Roozbeh Bonyadi

Temperature and Switching Rate Dependence of Crosstalk in Si-IGBT and SiC Power Modules

The temperature and dV/dt dependence of crosstalk has been analyzed for Si-IGBT and SiC-MOSFET power modules. Due to a smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot-through currents compared with similarly rated Si-IGBT modules in spite of switching with a higher dV/dt and with a lower threshold voltage. However, due to high voltage overshoots and ringing from the SiC Schottky diode, SiC modules exhibit higher shoot-through energy density and induce voltage oscillations in the dc link. Measurements show that the shoot-through current exhibits a positive temperature coefficient for both technologies, the magnitude of which is higher for the Si-IGBT, i.e., the shoot-through current and energy show better temperature stability in the SiC power module. The effectiveness of common techniques of mitigating shoot-through, including bipolar gate drives, multiple gate resistance switching paths, and external gate-source and snubber capacitors, has been evaluated for both technologies at different temperatures and switching rates. The results show that solutions are less effective for SiC-MOSFETs because of lower threshold voltages and smaller margins for negative gate bias on the SiC-MOSFET gate. Models for evaluating the parasitic voltage have also been developed for diagnostic and predictive purposes. These results are important for converter designers seeking to use SiC technology.

An Analysis of the Switching Performance and Robustness of Power MOSFETs Body Diodes: A Technology Evaluation

The tradeoff between the switching energy and electro-thermal robustness is explored for 1.2-kV SiC MOSFET, silicon power MOSFET, and 900-V CoolMOS body diodes at different temperatures. The maximum forward current for dynamic avalanche breakdown is decreased with increasing supply voltage and temperature for all technologies. The CoolMOS exhibited the largest latch-up current followed by the SiC MOSFET and silicon power MOSFET; however, when expressed as current density, the SiC MOSFET comes first followed by the CoolMOS and silicon power MOSFET. For the CoolMOS, the alternating p and n pillars of the superjunctions in the drift region suppress BJT latch-up during reverse recovery by minimizing lateral currents and providing low-resistance paths for carriers. Hence, the temperature dependence of the latch-up current for CoolMOS was the lowest. The switching energy of the CoolMOS body diode is the largest because of its superjunction architecture which means the drift region have higher doping, hence more reverse charge. In spite of having a higher thermal resistance, the SiC MOSFET has approximately the same latch-up current while exhibiting the lowest switching energy because of the least reverse charge. The silicon power MOSFET exhibits intermediate performance on switching energy with lowest dynamic latching current.

Compact Electrothermal Reliability Modeling and Experimental Characterization of Bipolar Latchup in SiC and CoolMOS Power MOSFETs

In this paper, a compact dynamic and fully coupled electrothermal model for parasitic BJT latchup is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latchup can be triggered by body-diode reverse-recovery hard commutation with high dV/dt or from avalanche conduction during unclamped inductive switching. In the case of body-diode reverse recovery, the base current that initiates BJT latchup is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the antiparallel p-i-n body diode. For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latchup, whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latchup during reverse recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of benchmarking the robustness of power MOSFETs.

The Effect of Electrothermal Nonuniformities on Parallel Connected SiC Power Devices Under Unclamped and Clamped Inductive Switching

Nonuniformities in the electrothermal characteristics of parallel connected devices reduce overall reliability since power is not equally dissipated between the devices. Furthermore, a nonuniform rate of operational degradation induces electrothermal variations thereby accelerating the development of failure. This paper uses simulations and experiments to quantitatively and qualitatively investigate the impact of electrothermal variations on the reliability of parallel connected power devices under unclamped inductive switching (UIS) conditions. This is especially pertinent to SiC where small die areas mean devices are often connected in parallel for higher current capability. Measurements and simulations show that increasing the variation in the initial junction temperatures and switching rates between parallel connected devices under UIS reduces the total sustainable avalanche current by 10%. It is seen that the device with the lower junction temperature and lower switching rate fails. The measurements also show that the maximum sustainable avalanche energy for a given variation in junction temperature and switching rate increases with the avalanche duration, meaning that the effect of electrothermal variation is more critical with high power (high current and low inductor) UIS pulses compared with high energy (low current and high inductance) pulses. These results are important for condition monitoring and reliability analysis.

Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS

Differences in the thermal and electrical switching time constants between parallel-connected devices cause imbalances in the power and temperature distribution, thereby reducing module robustness. In this paper, the impact of electrothermal variations (gate and thermal resistance) between parallel-connected devices on module robustness is investigated for 900-V-CoolMOS and 1.2-kV-SiC MOSFETs under clamped inductive switching (CIS) and unclamped inductive switching (UIS). Under CIS, the difference in the steady-state junction temperature (ΔTJ) and switching energy (ΔESW) between the parallel-connected devices for a given difference in the gate and thermal resistance (ΔRG and ΔRTH) is used as the metric for determining robustness to electrothermal variations, i.e., how well the devices maintain uniform temperature inspite of switching with different rates and thermal resistances. Under UIS conditions, the change in the maximum avalanche current/energy prior to device failure as a function of the ΔTJ and ΔRG between the parallel-connected devices is used as the metric. Under both CIS and UIS, SiC devices show better performance with minimal negative response to electrothermal variations between the parallel-connected devices. Finite-element models have also been performed showing the dynamics of BJT latch-up during UIS for different technologies.

Investigating the reliability of SiC MOSFET body diodes using Fourier series modelling

Using the Fourier series solution to the ambipolar diffusion equation, the robustness of the body diodes of SiC MOSFETs during reverse recovery has been studied. Parasitic bipolar latch-up during the reverse recovery of the body diode is a possible if there is sufficient base current and voltage drop across the body resistance to forward bias the parasitic BJT. SiC MOSFETs have very low carrier lifetime and thin epitaxial drift layers, which means that the dV/dt during the recovery of the body diode can be quite high. This dV/dt coupled with the parasitic drain-to-body capacitance can cause a body current. The paper introduces a new way of assessing the reliability of SiC MOSFETs during the reverse recovery of the body diode. The impact of switching rates, parasitic inductances and carrier lifetime on the activation of the parasitic BJT has been studied.

Characterization of 4H-SiC PiN Diodes Formed on Defects Identified by PL Imaging

In this paper the results of a study in which the surface quality of 30, 35 and 110 µm 4H-SiC epitaxial layers from different manufacturers are evaluated using AFM and photoluminescence (PL) imaging. PiN diodes are then intentionally fabricated on triangular defects and polytypes grains which are formed, in order to understand their impact on the resulting electrical characteristics, which includes on-state behaviour, turn-on characteristics and reverse leakage current behaviour. The results indicate that the defects form a high resistance short through the p-type anode. This results in higher leakage current, well over 108 times higher than the devices formed off-defect. PiN diodes fabricated on-defect also suffered from soft breakdown unlike those off-defect.

Physics-based modelling and experimental characterisation of parasitic turn-on in IGBTs

As power electronic engineers increase the switching speed of voltage source converters for the purpose of higher power density, the dI/dt and dV/dt across the power semiconductors increases as well. A well-known adverse consequence of high dV/dt is parasitic turn-on of the power device in the same phase leg as the device being triggered. This causes a short circuit with high shoot-through current, high instantaneous power dissipation and possibly device degradation and destruction. It is critical for converter designers to be able to accurately predict this phenomenon through diagnostic and predictive modelling. In this paper, a physics-based device and circuit model is presented together with experimental results on parasitic turn-on of IGBTs in voltage source converters. Because the model is physics based, it produces more accurate results compared with compact circuit models like SPICE and other circuit models that use lumped parameters. The discharge of the Miller capacitance is simulated as a voltage dependent depletion capacitance and an oxide capacitance as opposed to a lumped capacitor. The model presented accurately simulates IGBT tail currents, PiN diode reverse recovery and the non-linear miller capacitance all of which cannot be solved by lumped parameter compact models. This is due to the fact that the IGBT current in the model is calculated using the Fourier series based re-construction of the ambipolar diffusion equation and the miller capacitances are calculated using fundamental device physics equations. This paper presents a physics-based device and circuit model for parasitic turn-on in silicon IGBTs by numerically modelling the minority carrier distribution profile in the drift region. The model is able to accurately replicate the transient waveforms by avoiding the use of lumped parameters normally used in compact models.

Comparative electrothermal analysis between SiC Schottky and silicon PiN diodes: Paralleling and thermal considerations

In power modules with high current ratings where several devices are required for parallel connection, electrothermal balance between the parallel devices is a very important consideration. This paper investigates the impact of electrothermal imbalance between parallel connected devices on the thermal stability of the parallel pair. Under investigation are parallel connected 600 V silicon PiN and silicon carbide Schottky diodes. The electrothermal imbalance between the parallel devices was introduced by setting different initial junction temperatures and using different thermal boundary conditions i.e. different case temperatures. The effect of the diode technology on the thermal stresses of the complementing transistor is also assessed. The results show that silicon PiN diodes operate at lower junction temperatures because of the higher zero-temperature coefficient points in the forward current characteristics, however, the complementing MOSFETs are more thermally stressed since the reverse recovery of the diode causes current overshoots in the complementing transistor. It is also shown that SiC Schottky diodes exhibit more electrothermally stable operation under electrothermal imbalance when connected in parallel. Parallel connected SiC Schottky diodes with different initial junction temperatures and different thermal boundary conditions (case temperatures) exhibit better temperature convergence/stability compared to silicon PiN diodes. The temperature convergence in parallel SiC Schottky diode pairs is due to the lower Zero-Temperature Coefficient (ZTC) point compared with the PiN diode pairs, which means more equal current sharing in parallel SiC diodes.

Compact electrothermal models for unbalanced parallel conducting Si-IGBTs

For high current applications, silicon IGBTs are normally connected in parallel to deliver the required current ratings. The devices are normally designed to have identical electrothermal parameters for equal current and power sharing. However, over the mission profile of the device, non-uniform degradation of the electro-thermal properties like solder delamination or gate contact resistance as well as unequal heat extraction from the heat sink, can cause the parallel connected IGBTs to have different electrothermal properties. In this paper, a compact and accurate electro-thermal model for parallel connected IGBTs has been developed and validated by experimental measurements.