Olayiwola M. Alatise

The Impact of Parasitic Inductance on the Performance of Silicon–Carbide Schottky Barrier Diodes

1200V/300A silicon carbide Schottky barrier diode (SiC SBD) and Si pin diode modules have been tested as free-wheeling diodes under conditions of clamped inductive switching over a temperature range between -40 °C and 125 °C. Over the temperature range, the turn-OFF switching energy increases by 100% for the Si pin diode, whereas that of the SiC diode is temperature invariant and is 50% less than that of the Si pin diode at 125°C. However, the SiC SBD suffers from ringing/oscillations due to an underdamped response to an RLC circuit formed among the diode depletion capacitance, parasitic inductance, and diode resistance. These oscillations contribute to additional power losses that cause the SiC SBDs to be outperformed by the Si pin diodes at -40 °C and 0 °C. The higher depletion capacitance and lower series resistance of the SiC SBD contribute to a lower damping factor compared to the Si device. Furthermore, the positive temperature coefficient of the ON-state resistance in silicon contributes to better damping at high power levels, whereas the temperature invariance of the ON-state resistance in SiC means the oscillations persist at high temperatures. SPICE simulations and experimental measurements have been used to validate analytical expressions that have been developed for the circuit damping and oscillation frequency.

Temperature and Switching Rate Dependence of Crosstalk in Si-IGBT and SiC Power Modules

The temperature and dV/dt dependence of crosstalk has been analyzed for Si-IGBT and SiC-MOSFET power modules. Due to a smaller Miller capacitance resulting from a smaller die area, the SiC module exhibits smaller shoot-through currents compared with similarly rated Si-IGBT modules in spite of switching with a higher dV/dt and with a lower threshold voltage. However, due to high voltage overshoots and ringing from the SiC Schottky diode, SiC modules exhibit higher shoot-through energy density and induce voltage oscillations in the dc link. Measurements show that the shoot-through current exhibits a positive temperature coefficient for both technologies, the magnitude of which is higher for the Si-IGBT, i.e., the shoot-through current and energy show better temperature stability in the SiC power module. The effectiveness of common techniques of mitigating shoot-through, including bipolar gate drives, multiple gate resistance switching paths, and external gate-source and snubber capacitors, has been evaluated for both technologies at different temperatures and switching rates. The results show that solutions are less effective for SiC-MOSFETs because of lower threshold voltages and smaller margins for negative gate bias on the SiC-MOSFET gate. Models for evaluating the parasitic voltage have also been developed for diagnostic and predictive purposes. These results are important for converter designers seeking to use SiC technology.

An Evaluation of Silicon Carbide Unipolar Technologies for Electric Vehicle Drive-Trains

Voltage sourced converters (VSCs) in electric vehicle (EV) drive-trains are conventionally implemented by silicon Insulated Gate Bipolar Transistors (IGBTs) and p-i-n diodes. The emergence of SiC unipolar technologies opens up new avenues for power integration and energy conversion efficiency. This paper presents a comparative analysis between 1.2-kV SiC MOSFET/Schottky diodes and silicon IGBT/p-i-n diode technologies for EV drive-train performance. The switching performances of devices have been tested between -75 °C and 175 °C at different switching speeds modulated by a range of gate resistances. The temperature impact on the electromagnetic oscillations in SiC technologies and reverse recovery in silicon bipolar technologies is analyzed, showing improvements with increasing temperature in SiC unipolar devices whereas those of the silicon-bipolar technologies deteriorate. The measurements are used in an EV drive-train model as a three-level neutral point clamped VSC connected to an electric machine where the temperature performance, conversion efficiency and the total harmonic distortion is studied. At a given switching frequency, the SiC unipolar technologies outperform silicon bipolar technologies showing an average of 80% reduction in switching losses, 70% reduction in operating temperature and enhanced conversion efficiency. These performance enhancements can enable lighter cooling and more compact vehicle systems.

The Impact of Repetitive Unclamped Inductive Switching on the Electrical Parameters of Low-Voltage Trench Power nMOSFETs

The impact of hot-carrier injection (HCI) due to repetitive unclamped inductive switching (UIS) on the electrical performance of low-voltage trench power n-type MOSFETs (nMOSFETs) is assessed. Trench power nMOSFETs with 20- and 30-V breakdown voltage ratings in TO-220 packages have been fabricated and subjected to over 100 million cycles of repetitive UIS with different avalanche currents IAV at a mounting base temperature TMB of 150°C. Impact ionization during avalanche conduction in the channel causes hot-hole injection into the gate dielectric, which results in a reduction of the threshold voltage VGSTX, as the number of avalanche cycles N increases. The experimental data reveal a power-law relationship between the change in the threshold voltage ΔVGSTX and N. The results show that the power-law prefactor is directly proportional to the avalanche current. After 100 million cycles, it was observed in the 20-V rated MOSFETs that the power-law prefactor increased by 30% when IAV was increased from 160 to 225 A, thereby approximating a linear relationship. A stable subthreshold slope with avalanche cycling indicates that interface trap generation may not be an active degradation mechanism. The impact of the cell pitch on avalanche ruggedness is also investigated by testing 2.5- and 4- m cell-pitch 30-V rated MOSFETs. Measurements showed that the power-law prefactor reduced by 40% when the cell pitch was reduced by 37.5%. The improved VGSTX stability with the smaller cell-pitch MOSFETs is attributed to a lower avalanche current per unit cell resulting in less hot-hole injection and, hence, smaller VGSTX shift. The 2.5-m cell-pitch MOSFETs also show 25% improved on -state resistance RDSON, better RDSON stability, and 20% less subthreshold slope compared with the 4-m cell-pitch MOSFETs, although with 100% higher initial IDSS and less IDSS stability with avalanche cycling. These results are important for manufacturers of automotive MOSFETs where multiple avalanche occurrences over the lifetime of the MOSFET are expected.

An Analysis of the Switching Performance and Robustness of Power MOSFETs Body Diodes: A Technology Evaluation

The tradeoff between the switching energy and electro-thermal robustness is explored for 1.2-kV SiC MOSFET, silicon power MOSFET, and 900-V CoolMOS body diodes at different temperatures. The maximum forward current for dynamic avalanche breakdown is decreased with increasing supply voltage and temperature for all technologies. The CoolMOS exhibited the largest latch-up current followed by the SiC MOSFET and silicon power MOSFET; however, when expressed as current density, the SiC MOSFET comes first followed by the CoolMOS and silicon power MOSFET. For the CoolMOS, the alternating p and n pillars of the superjunctions in the drift region suppress BJT latch-up during reverse recovery by minimizing lateral currents and providing low-resistance paths for carriers. Hence, the temperature dependence of the latch-up current for CoolMOS was the lowest. The switching energy of the CoolMOS body diode is the largest because of its superjunction architecture which means the drift region have higher doping, hence more reverse charge. In spite of having a higher thermal resistance, the SiC MOSFET has approximately the same latch-up current while exhibiting the lowest switching energy because of the least reverse charge. The silicon power MOSFET exhibits intermediate performance on switching energy with lowest dynamic latching current.

Improved Electrothermal Ruggedness in SiC MOSFETs Compared With Silicon IGBTs

A 1.2-kV/24-A SiC-MOSFET and a 1.2-kV/30-A Si-Insulated gate bipolar transistor (IGBT) have been electrothermally stressed in unclamped inductive switching conditions at different ambient temperatures ranging from -25 °C to 125 °C. The devices have been stressed with avalanche currents at their rated currents and 40% higher. The activation of the parasitic bipolar junction transistor (BJT) during avalanche mode conduction results from the increased body resistance causing a voltage drop between the source and body, greater than the emitter-base voltage of the parasitic BJT. Because the BJT current and temperature relate through a positive feedback mechanism, thermal runaway results in the destruction of the device. It is shown that the avalanche power sustained before the destruction of the device increases as the ambient temperature decreases. SiC MOSFETs are shown to be able to withstand avalanche currents equal to the rated forward current at 25 °C, whereas IGBTs cannot sustain the same electrothermal stress. SiC MOSFETs are also shown to be capable of withstanding avalanche currents 40% above the rated forward current though only at reduced temperatures. An electrothermal model has been developed to explain the temperature dependency of the BJT latchup, and the results are supported by finite-element models.

The Impact of Temperature and Switching Rate on the Dynamic Characteristics of Silicon Carbide Schottky Barrier Diodes and MOSFETs

Silicon carbide Schottky barrier diodes (SiC-SBDs) are prone to electromagnetic oscillations in the output characteristics. The oscillation frequency, peak voltage overshoot, and damping are shown to depend on the ambient temperature and the metal-oxide- semiconductor field-effect transistor (MOSFET) switching rate (dIDS/dt). In this paper, it is shown experimentally and theoretically that dIDS/dt increases with temperature for a given gate resistance during MOSFET turn-on and reduces with increasing temperature during turn-off. As a result, the oscillation frequency and peak voltage overshoot of the SiC-SBD increases with temperature during diode turn-off. This temperature dependence of the diode ringing reduces at higher dIDS/dt and increases at lower dIDS/dt. It is also shown that the rate of change of dIDS/dt with temperature (d2IDS/dtdT) is strongly dependent on RG and using fundamental device physics equations, this behavior is predictable. The dependence of the switching energy on dIDS/dt and temperature in 1.2-kV SiC-SBDs is measured over a wide temperature range (-75 °C to 200 °C). The diode switching energy analysis shows that the losses at low dIDS/dt are dominated by the transient duration and losses at high dIDS/dt are dominated by electromagnetic oscillations. The model developed and results obtained are important for predicting electromagnetic interference, reliability, and losses in SiC MOSFET/SBDs.

Low Stress Cycle Effect in IGBT Power Module Die-Attach Lifetime Modeling

Operational management for reliability of power electronic converters requires sensitive condition monitoring and accurate lifetime modeling. This study adds to the second aspect by examining the effect of cyclic junction temperature variations ΔTj of low amplitude in different stages of the power module ageing process. It is found that such relatively minor stress cycles, which happen frequently during normal operation, may not be able to directly initiate a crack but can contribute to the development of damage due to stress concentration. This agrees with the observation that the ageing process tends to accelerate toward the end of life. This study investigates the dependence of the ageing effect on the amplitude of ΔTj, the mean junction temperature T,,,, and the present health condition of the module, and proposes a lifetime model focusing on die-attach solder fatigue. It is assumed that the future-ageing process is independent of the operational history that has led to the current state of health. The model is intended for operational management of converter systems that are subjected to frequent low ΔTj stress cycles and are supposed to be in service reliably for a long time with a slow ageing process. Experimental results validate the model.

Reliability of Repetitively Avalanched Wire-Bonded Low-Voltage Discrete Power Trench n-MOSFETs

This paper, for the first time, investigates the reliability of wire-bonded low-voltage discrete power trench n-MOSFETs that have been subjected to repetitive unclamped inductive switching (RUIS). Automotive MOSFETs driving inductive loads may be subjected to RUIS; hence, there is a need to characterize the failure mechanisms in such applications. The failure mechanisms of repetitively avalanched wire-bonded MOSFETs are shown to be wire-bond lift-off and source metal degradation/fatigue due to thermomechanical stress cycling. Temperature excursions from avalanche pulses cause thermomechanical stresses on the wire-bond/source-metal interface as a result of differences in thermal expansion coefficients between silicon and aluminum. Trench MOSFETs exhibited an average of 10% increase in on-state resistance due to source metal fatigue after 100 million cycles of repetitive avalanche. The number of cycles to failure is investigated as a function of the avalanched induced temperature changes and is shown to follow the Coffin-Manson law. These results are important for designers of automotive systems since they are capable of predicting the long-term reliability of wire-bonded discrete power semiconductor components.

Understanding Linear-Mode Robustness in Low-Voltage Trench Power MOSFETs

The high-temperature electrothermal stability and linear-mode robustness of low-voltage discrete power trench MOSFETs are assessed. The linear-mode robustness is shown to be dependent on the positive temperature coefficient of the subthreshold diffusion current and the MOSFET gain factor. The datasheet threshold voltage temperature coefficient (V GSTX TC) of a power MOSFET is important because it correlates with the linear-mode robustness and the zero-temperature-coefficient (ZTC) point of the device. The impact of the MOSFET active area and the cell pitch on the V GSTX TC is experimentally assessed on fabricated devices. It is shown that the magnitude of the V GSTX TC increases as the MOSFET active area increases, whereas it reduces as the cell pitch increases. The drain voltage at the onset of thermal runaway is shown to increase as the V GSTX TC reduces for the same active area, thereby making the V GSTX TC an indicator of linear-mode robustness. Although the gate voltage at the ZTC point and the magnitude of the V GSTX TC increase with the MOSFET active area, the reduced thermal resistance improves the linear-mode robustness. The implication is that improved device performance in terms of lower specific on-state resistance ( R SPEC in ohm-square millimeter) is at the expense of linear-mode robustness of the power MOSFET since lower R SPEC devices have higher gain factors and higher currents are delivered at weaker inversion levels (and therefore contain higher proportions of subthreshold diffusion currents). In designing power MOSFETs, these parameters must be taken into consideration so as to minimize high-temperature instability and improve linear-mode robustness.