Jose Cruz-Albrecht

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme.

Energy-Efficient Neuron, Synapse and STDP Integrated Circuits

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

A scalable neural chip with synaptic electronics using CMOS integrated memristors

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Neuromorphic Adaptive Plastic Scalable Electronics: Analog Learning Systems

This article provides an overview of the HRL Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) project and progress made thus far. The multifaceted SyNAPSE program seeks to advance the state of the art in biological algorithms and in developing a new generation of neuromorphic electronic machines necessary for the efficient implementation of these algorithms by drawing inspiration from biology.The fundamental premise of the HRL team to develop brain architecture and related tools has been to recognize that there was a sequence of evolutionary events by which the brain architecture evolved from a primitive brain into a modern brain.

Programming Time-Multiplexed Reconfigurable Hardware Using a Scalable Neuromorphic Compiler

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

CMOS-integrated memristors for neuromorphic architectures

High-density memristor arrays are integrated on complementary metal-oxide-semiconductor (CMOS) substrates for neuromorphic circuit architectures. Advancing previously-reported work on Ag-filament memristor arrays [1], memristor operation is shown both in conjunction with CMOS multiplexer (MUX) circuits and in a “direct-access” configuration in which cross-bars are directly connected via CMOS interconnects to probe pads. The memristor arrays provide a high-density analog memory technology intended for CMOS-based neuromorphic architectures, Fig. 1 and [2]. Electrical data is shown for cross-bar arrays fabricated at 400-nm pitch with each memristor exhibiting intrinsic rectifying behavior, a beneficial feature for array operation. Forward-reverse-bias current ratios exceed 103 at ±1.5 V. Devices are programmed to four distinct resistance states, demonstrating utility as an analog memory with an effective number of bits (ENOB) of 2. Devices are fabricated and characterized across a 2” 180-nm-node CMOS wafer. Fabrication results are shown for 100-nm-pitch cross-bar arrays which enable effective bit densities greater than 1010 bits/cm2.

Neuromorphic and early warning behavior-based authentication for mobile devices

Finding the balance between security, privacy, and usability for mobile authentication has been an active area of research for the past several years. Many researchers have taken advantage of the availability of multiple sensors on mobile devices and have used these data to train classifiers to authenticate users. For example, implicit authentication algorithms have been developed based on behavior patterns identified from a combination of sensors including location, co-location, application usage, biometric measurements, continuity of interaction between the user and the phone, and possession of the phone [1,2,3,4,5]. Furthermore, the onboard sensors of mobile devices have previously been used to identify users based on touch [6] and fusions of touch and speech inputs [7]. However, a system utilizing low-power onboard electronics for anomaly detection and user classification is lacking. Here, we report on the performance of two subsystems tested in a controlled use scenario to classify and authenticate users of a mobile device. The overall system utilizes two subsystems for anomaly detection and user classification: (1) a neuromorphic chip for continuous, low-power, online monitoring and classification, and (2) an early warning system (EWS) algorithm for longer duration time-series behavioral and biometric classification.

Criticality as a Set-Point for Adaptive Behavior in Neuromorphic Hardware.

Neuromorphic hardware are designed by drawing inspiration from biology to overcome limitations of current computer architectures while forging the development of a new class of autonomous systems that can exhibit adaptive behaviors. Several designs in the recent past are capable of emulating large scale networks but avoid complexity in network dynamics by minimizing the number of dynamic variables that are supported and tunable in hardware. We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems. It has been widely demonstrated that criticality appears to be the default state of the brain and manifests in the form of spontaneous scale-invariant cascades of neural activity. Experiment, theory and recent models have shown that neuronal networks at criticality demonstrate optimal information transfer, learning and information processing capabilities that affect behavior. In this perspective article, we argue that understanding how large scale neuromorphic electronics can be designed to enable emergent adaptive behavior will require an understanding of how networks emulated by such hardware can self-tune local parameters to maintain criticality as a set-point. We believe that such capability will enable the design of truly scalable intelligent systems using neuromorphic hardware that embrace complexity in network dynamics rather than avoiding it.

Neuromorphic mixed-signal circuitry for Asynchronous Pulse Processing

We demonstrate a software reconfigurable mixed-signal Printed Circuit Board (PCB) prototype and a custom mixed-signal Application Specific Integrated Circuit (ASIC) prototype of a cognitive signal processor using neuromorphic methods to perform adaptive nonlinear filtering based real-time wideband signal processing algorithms. The cognitive processor effectively implements a trending computing paradigm called Reservoir Computer (RC). Hardware implementation of the RC is achieved by a novel analog signal processor architecture called the Asynchronous Pulse Processor (APP).

Neuromorphic and Early Warning behavior-based authentication in common theft scenarios

With increased rates of smartphone theft over the past decade, mobile authentication systems that operate on a continual basis are a necessity to meet increasing demands for user privacy, device usage, and authentication accuracy. Rather than forcing end users to continually self-authenticate via password pins or through other means on a time-interval basis [2–7], a system that continuously authenticates users provides a more frictionless relationship between a users device and its physical security. Such a system, if effectively operating on a low-powered, unobtrusive, and secure basis, would make it viable for most consumer mobile devices. In this paper, we build upon our work in [1] to provide a novel authentication scheme that meets these requirements for a commonly adopted system. Our system, iSentinel, hopes to provide an unobtrusive, low-powered solution for detecting and responding to common theft scenarios by continuously authenticating mobile devices in use cases such as walking, texting, and driving.