Donald A. Hitko

A low power (45mW/latch) static 150GHz CML divider

Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipates only 45mW per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27/spl deg/C ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30/spl deg/C was established across the wafer.

Heterogeneous wafer-scale integration of 250nm, 300GHz InP DHBTs with a 130nm RF-CMOS technology

The performance advantages of InP based devices over silicon devices are well known, but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. A large commercial market, however, has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both of these technologies in order to enable a new class of high performance ICs. This work demonstrates the wafer scale integration of an advanced 250 nm, 300 GHz fT/fMAX InP DHBT technology with IBMs 130 nm RF-CMOS technology (CMRF8SF). Such integration allows the rapid adoption of more advanced CMOS and InP DHBT technology generations.

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 /spl times/ 6 /spl mu/m/sup 2/ emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f/sub T/ of 252 GHz and f/sub MAX/ of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 /spl mu/A, and a peak dc /spl beta/ of 36 were measured.

Characterization and modeling of thermal effects in sub-micron InP DHBTs

S-parameter measurements performed on 400GHz InP DHBTs, with 250nm and 400nm wide emitters, show that an 8-10% increase in peak f/sub T/ can be achieved when the ambient temperature is reduced from +25/spl deg/C to -50/spl deg/C. This strong temperature dependence of device performance indicates that thermal modeling plays a critical role in device and circuit design. Using the Synopsys/spl reg/ DESSIS simulator, a 3D thermal model was calibrated to these sub-micron 400GHz InP DHBTs for use in technology development. The 3D model is sufficiently complex to allow the thermal de-embedding of pads; projection of R/sub TH/ to higher dissipated powers; and estimates of cooperative heating. These three features allow the 3D model to go beyond the data that can be acquired by direct measurement, and lead to a more accurate value of R/sub TH/ for compact models.

State of the art low power (42 mW per flip-flop) 150 GHz+ CML static divider implemented in scaled 0.2 m emitter-width InP DHBTs

Recent development efforts in scaling InP DHBT technologies have pushed transistor cutoff frequencies beyond 400 GHz and demonstrated static flip-flop circuits clocking in excess of 150 GHz. Despite the impressive clock rates, obtaining these operating speeds has required an increase in collector current densities that has largely offset the power reductions achieved to date in scaling the emitter area of the devices in these technologies. Further lateral scaling is required to manage thermal concerns and enable logic circuits of greater complexity. Measured results are shown of a static frequency divider realized in a 0.2 m InP/InGaAs/InP DHBT technology that lowers flip-flop power dissipation to 42 mW while clocking at 150 GHz rates. This represents a factor of two improvement in the state of the art power-delay product over previously reported logic circuits operating at >120 GHz clock rates

Experimental method to thermally deembed pads from R/sub TH/ measurements

Both compound semiconductor and silicon-based bipolar junction transistors or heterojunction bipolar transistors (HBTs) require the efficient removal of heat in order to achieve a maximum level of performance and reliability. In order to satisfy both of these criteria, the electrothermal behavior of each device must be captured in a compact model. The model parameter that determines the junction temperature is R TH, the thermal resistance. Experimental methods to determine RTH often require a relatively small device with a large R TH to be attached to a set of relatively large metal pads with a low RTH. The pads act as a thermal shunt to the substrate and artificially lower the measured RTH. In order to obtain a suitable RTH value for a device located in an IC, the pads must be deembedded from the measured data, much like pad deembedding for an S-parameter measurement. Test structures with various width metal traces between the emitter pad and devices emitter have been fabricated in a 200-GHz InP double HBT process. A method of using the measured RTH of these structures and a simple resistive network model to deembed the pads is presented. It is shown that deembedded values can be as much as 30% higher than the measured RTH

First demonstration of sub-0.25/spl mu/m-width emitter InP-DHBTs with > 400 GHz f/sub t/ and > 400 GHz f/sub max/

We report performance of sub-0.25/spl mu/m emitter-width InP/InGaAs/InP DHBTs. These are the smallest emitter-width III-V devices reported to date. Measured ft/fmax performance of 406GHz/423GHz is the first ever reported for a sub-0.25/spl mu/m emitter-width DHBT and among the fastest for any DHBTs. With the peak f/sub t/ and f/sub max/ performance occurring at I/sub c/ = 8mA (V/sub ce/ /spl sim/ 1.25V), this is the lowest power consumption DHBT ever reported with state of the art cutoff frequencies. The as-patterned emitter contact metal width for these devices was 0.25 /spl mu/m and the width of the emitter at the emitter-base junction is less than 0.25 /spl mu/m owing to undercutting of the underlying emitter semiconductor. When comparing with 0.4 /spl mu/m emitter width DHBTs, we find that 0.4 /spl mu/m device has the higher measured f/sub t/, /spl sim/ 420GHz, due to the lower emitter resistance for that emitter layout. F/sub max/ was highest for the 0.25/spl mu/m emitter devices due to lower base-collector mesa capacitance, C/sub bc/, which results from the reduced mesa width. We find this behavior to be consistent with scaling tradeoffs in the design of ultra-fast DHBTs.

Patterned n+ implant into InP substrate for HBT subcollector

We demonstrate molecular-beam epitaxy (MBE)-grown heterojunction bipolar transistors (HBTs) on InP substrates with a patterned implant n+ subcollector below the epitaxial layers. Device layers grown on implanted/annealed substrates were of similar quality to those on virgin InP. Maximum f/sub t/ and f/sub max/ of 240 and 310 GHz were obtained. We present the process flow, details of the ion implantation, layer characterization, and device results.

Non-Foster Circuit Adaptation for Stable Broadband Operation

A non-Foster circuit adaptation algorithm has been developed and demonstrated in a printed circuit board by using commercial off-the-shelf components. This algorithm enables adaptive stabilization of non-Foster circuits (NFCs) to achieve broadband operation, such as matching of electrically small receive antennas, hence avoiding potential oscillation and undesirable signal emission. The demonstrated system has been fabricated in a 6.4 ×8.9 cm2 4 layer FR4 PCB. Together with a fabricated NFC board, it achieves stable wideband matching for a 15 cm long monopole antenna under different environment conditions, such as an additional loading of a Cu metallic sheet in a proximate location to the antenna. The demonstration indicates the effectiveness of the proposed NFC adaptation algorithm and paves the way for broad applications of NFCs without stability concerns.