J.F. Jensen

A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology

This paper presents a second-order delta-sigma (/spl Delta//spl Sigma/) modulator fabricated in a 70 GHz (f/sub T/), 90 GHz (f/sub max/) AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates. The modulator is a continuous time, fully differential circuit operated from /spl plusmn/5 volt supplies and dissipates 1 W. At a sample rate of 3.2 GHz and a signal bandwidth of 50 MHz (OSR=32100 MSPS Nyquist rate) the modulator demonstrates a Spur Free Dynamic Range (SFDR) of 71 dB (12-b dynamic range). The modulator achieves the ideal signal-to-noise ratio (SNR) of 55 dB for a second-order modulator at an oversampling ratio (OSR) of 32. The design of a digital decimation filter for this modulator is complete and the filter is currently in fabrication in the same technology. This work demonstrates the first /spl Delta//spl Sigma/ modulator in III-V technology with ideal performance and provides the foundation for extending the use of /spl Delta//spl Sigma/ modulator analog-to-digital converters (ADCs) to radio frequencies (RF). >

Ultra-high-speed digital circuit performance in 0.2- mu m gate-length AlInAs/GaInAs HEMT technology

The fabrication of fifteen-stage ring oscillators and static flip-flop frequency dividers with 0.2- mu m gate-length AlInAs/GaInAs HEMT technology is described. The fabricated HEMT devices within the circuits demonstrated a g/sub m/ transconductance of 750 mS/mm and a full-channel current of 850 mA/mm. The measured cutoff frequency of the device is 120 GHz. The shortest gate delay measured for buffered-FET-logic (BFL) ring oscillators at 300 K was 9.3 ps at 66.7 mW/gate (fan-out=1); fan-out sensitivity was 1.5 ps per fanout. The shortest gate delay measured for capacitively enhanced logic (CEL) ring oscillators at 300 K was 6.0 ps at 23.8 mW/gate (fan-out=1) with a fan-out sensitivity of 2.7 ps per fan-out. The CEL gate delay reduced to less than 5.0 ps with 11.35-mW power dissipation when measured at 77 K. The highest operating frequency for the static dividers was 26.7 GHz at 73.1 mW and 300 K.<<ETX>>

39.5-GHz static frequency divider implemented in AlInAs/GaInAs HBT technology

A static divide-by-four frequency divider operating at 39.5-GHz input frequency is reported. Graded emitter-base junction AlInAs/GaInAs heterojunction bipolar transistor (HBT) technology lattice-matched to InP substrates has been used to implement the divider. The graded junction HBTs feature unity gain cutoff frequency and maximum frequency of oscillation of 130 GHz and 91 GHz, respectively. The devices have a very low turn-on voltage of about 0.7 V at collector current density of 5*10/sup 4/ A/cm/sup 2/. The divider operated at a power supply voltage of -3 V and consumes a total DC power of 425 mW, corresponding to 77 mW per flip-flop.<<ETX>>

An InP-based HBT fab for high-speed digital, analog, mixed-signal, and optoelectronic ICs

Integrated circuits (ICs) utilizing indium phosphide based heterojunction bipolar transistors (HBTs) have set numerous speed and bandwidth records over the past several years. This paper describes the extension of that HBT IC technology to an IC fabrication capability which is quite versatile in being able to produce digital, analog, mixed signal, and optoelectronic ICs within the same process. This enables the fab line to quickly respond to varying demands. Three ICs are discussed which exemplify the capability of this fab: (1) a 7 GHz 12-bit accumulator; (2) a nearly ideal continuous-time-sampling second-order /spl Delta//spl Sigma/ modulator operating at a 3.2 GHz sample rate; and (3) a monolithic 4-channel optoelectronic receiver array capable of 20 Gb/s operation.

Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP /spl Delta//spl Sigma/) modulators. Bandpass modulators sampling at high IFs (/spl sim/100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP /spl Delta//spl Sigma/ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 80 GHz and a maximum frequency of oscillation (f/sub MAX/) of about 130 GHz. Operating from /spl plusmn/5-V power supplies, a fabricated 180-MHz IF fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (/spl sim/1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (/spl sim/60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements.

Self-aligned AlInAs-GaInAs heterojunction bipolar transistors and circuits

AlInAs-GaInAs heterojunction bipolar transistors (HBTs) and static flip-flop frequency dividers have been fabricated. An f/sub t/ and an f/sub max/ of 49 and 62 GHz, respectively, have been achieved in a device with a 2*5- mu m/sup 2/ emitter. Current-mode logic (CML) was used to implement static divide-by-two and divide-by-four circuits. The divide-by-two circuit operated at 15 GHz with 82-mW power dissipation for the single flip-flop. The divide-by-four circuit operated at 14.5 GHz with a total chip power dissipation of 444 mW.<<ETX>>

Reliability of AlInAs/GaInAs heterojunction bipolar transistors

The reliability of high-performance AlInAs/GaInAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE) is discussed. Devices with a base Be doping level of 5*10/sup 19/ cm/sup -3/ and a base thickness of approximately 50 nm displayed no sign of Be diffusion under applied bias. Excellent stability in DC current gain, device turn-on voltage, and base-emitter junction characteristics was observed. Accelerated life-test experiments were performed under an applied constant collector current density of 7*10/sup 4/ A/cm/sup 2/ at ambient temperatures of 193, 208, and 328 degrees C. Junction temperature and device thermal resistance were determined experimentally. Degradation of the base-collector junction was used as failure criterion to project a mean time to failure in excess of 10/sup 7/ h at 125 degrees C junction temperature with an associated activation energy of 1.92 eV. >

A 1.3-GHz IF digitizer using a 4/sup th/-order continuous-time bandpass /spl Delta//spl Sigma/ modulator

We present a 4/sup th/-order, 3-bit, 4.3 GHz continuous-time bandpass /spl Delta//spl Sigma/ modulator (CT-DSM) that can directly digitize a 1.3-GHz IF signal. We used the impulse-invariant transform to design the CT-DSM, which has a similar NTF (noise transfer function) as an idealized discrete-time modulator despite up to 1.6 clock delays in its feedback loop paths. The part was fabricated using InP HBT technology, and has a measured SNDR of 39 dB in a 200 MHz bandwidth.

The effects of base dopant diffusion on DC and RF characteristics of InGaAs/InAlAs heterojunction bipolar transistors

The effects of base p-dopant diffusion at junction interfaces of InGaAs/InAlAs HBTs with thin base thicknesses and high base dopings are reported. It is shown that HBTs with compositionally graded emitter-based (E-B) junctions are very tolerant to base dopant outdiffusion into the E-B graded region. The RF performance is nearly unaffected by the diffusion, and the DC current gain and E-B junction breakdown voltages are improved with finite Be diffusion into the E-B graded region.<<ETX>>

A low power (45mW/latch) static 150GHz CML divider

Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipates only 45mW per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27/spl deg/C ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30/spl deg/C was established across the wafer.