Jose Fontebasso Neto
Universidade Católica de Santos
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Jose Fontebasso Neto.
latin american symposium on circuits and systems | 2012
Jose Fontebasso Neto; Luiz Carlos Moreira; Wilhelmus A. M. Van Noije
This paper presents a fully integrated low-power 7th derivative Gaussian pulse generator for UWB applications designed in 180 nm CMOS technology. We propose a simple architecture based on parallel pulse generator blocks that produce Gaussian pulses, and a pulse shaping stage which adjusts each pulse amplitude individually. The whole circuit has been simulated and the results have demonstrated the circuit capability to operate like an impulse generator. The implemented circuit generates pulse envelopes of 944 ps width and maximum amplitude of 120 mVpp, an average power of 3.8 mW/pulse at 100 MHz PRF and about energy of 4.6 pJ/pulse. The circuit does not need any inductor leading to a very small area; therefore, the complete circuit occupies only 73×75 μm2 (without PADs). This pulse generator complies with FCC UWB spectral power mask.
sbmo/mtt-s international microwave and optoelectronics conference | 2015
Jose Fontebasso Neto; Luiz Carlos Moreira; Thiago Ferauche; Fatima Salete Correra; Wilhelmus A. M. Van Noije
This paper presents a fully integrated BPSK (Binary Phase Shift Keying) Transmitter Front End for Ultra-Wideband (UWB) applications, designed in 130 nm CMOS technology. A simple architecture based on parallel pulse generator blocks in parallel is proposed to produce 9th derivative Gaussian pulses. In addition to the pulse generator, the circuit comprises a passive balun circuit, a common source amplifier, and a BPSK modulator. The transmitter has been simulated and the results demonstrated the circuit capability to operate as a front end BPSK transmitter. The proposed circuit generates output pulse envelopes of width 0.8 ns and maximum amplitude of 40 mVpp, an average power consumption of 1.9 μW/pulse and energy of 1.6 fJ/pulse when fed with a 715 MHz clock and 100 MHz data sources. The whole circuit occupies 480 × 320 μm2 (without pads). This pulse generator complies with FCC UWB spectral power mask).
latin american symposium on circuits and systems | 2017
Luiz Carlos Moreira; Jose Fontebasso Neto; Thiago Ferauche; Guilherme Apolinario Silva Novaes; Emmanuel Torres Rios
A new circuit technique, the reconfigurable puise generator circuit is proposed to produce a puise width inversely proportional to the spectrum power bandwidth in the Impulse Radio Ultra-Wide Band (IR-UWB) circuits. The complete circuit was based on two pulse generator blocks using Positive Pulse Generator (PPG), and Negative Pulse Generator (NPG) to compose a rectangular waveform at the output. These pulse generators have been implemented with high impedance circuits and are selected by digital control signals. Thus, each block can be adjusted to generate up to eight sequential pulses per clock edge. The circuit was designed to use Binary Phase Shift Keying (BPSK) scheme for modulation and can change the frequency spectrum of the signal pulses. In addition, we implemented a voltage divider circuit using two transistors in parallel with a charge pump circuit to control the signal amplitude at the output. The proposed pulse generator circuit operates at a maximum operation frequency at 12 GHz. The pos-layout simulations were performed using LTSpice, and the results show a pulse amplitude of 160mV and an average power consumption of 11.3 fJ per pulse at lowest operating frequency and 85.3 fJ per pulse at highest operating frequency, for a Pulse Repetition Frequency (PRF) of 100MHz at 1.3V power supply voltage. The core chip size occupies a very small area of 210 μm × 75 μm (without PADs).
2016 IEEE MTT-S Latin America Microwave Conference (LAMC) | 2016
Jose Fontebasso Neto; Luiz Carlos Moreira; Fatima Salete Correra
This paper presents a simple equivalent electrical circuit model to represent spiral and cross inductors on CMOS Technology. The inductors were designed and simulated using Momentum/ADS from Keysight, and were fabricated on AMS 0.35 µm CMOS technology. Simulation data was used to develop a RLC model for the inductors, where the reactive elements are constant and the resistance depends on frequency. A linear equation was proposed to represent the frequency dependence of the inductors resistance. The simulated results of spiral and cross inductors were in good agreement with the model results. On chip measurements of the inductors were performed from 1 to 10 GHz using a network analyzer. The inductance and maximum quality factor obtained from the measured data were well predicted by the proposed model, which showed good precision on spite of its simplicity.
latin american symposium on circuits and systems | 2013
M. M. da Silva; Jose Fontebasso Neto; Luiz Carlos Moreira; Jacobus W. Swart
This paper presents a CMOS pixel motion detector based on a current-mode APS (Active Pixel Sensor) topology with wireless capability using an Impulse Radio - Ultra Wide Band (IR-UWB) in standard 0.35μm CMOS technology for applications in image sensor networks. A pixel was designed with a transmission gate to control one copier cell in order to compare different integration times. The pixel output is a digital signal proportional to the difference between the two currents. The proposed IR-UWB has a simple architecture, without inductors and carrier modulators. It is based on parallel pulse generator blocks that produce Gaussian pulses, and a pulse shaping stage which adjusts the pulse amplitude, below the FCC -41.3dBm floor. The transmitter exhibits as main characteristics: output pulse of 408ps wide at 4.90GHz, and voltage amplitude of 144mVpp, an average power is only of 7.15μW/pulse at 170MHz PRF (Pulse Repetition Frequency). The whole circuit has been simulated using LTSpice and the results demonstrate the circuit capability to operate as a motion detector. The complete circuit pixel occupies a very small area of 120μm × 115μm.
latin american symposium on circuits and systems | 2013
Luiz Carlos Moreira; Jose Fontebasso Neto; W.A.M. Van Noije; E. T. Rios
In this paper, a new design for an Impulse Radar UWB transmitter using an 180nm CMOS process is presented. A 2nd order derivative Gaussian pulse is generated using two Phase Detectors (PDs), which consist of an n-latch and a p-latch to generate a single UWB pulse without any filtering and matches the FCC mask. The Gaussian impulse achieves a very small pulse of 288ps width, 160mVpp amplitude, and consumes about 13μW/pulse. The circuit occupies only 36×42μm2 without PADs.
sbmo/mtt-s international microwave and optoelectronics conference | 2011
Luiz Carlos Moreira; Jose Fontebasso Neto; Wilhelmus A. M. Van Noije; Sergio Takeo Kofuji
This paper presents a design of an UWB PPM — Pulse Position Modulation transmitter based on a 1.8V, 0.18μm CMOS technology. We propose a pulse generator using modified Nand gate as a Phase Detector (PD) with an effective phase difference of 73ps. At the PD output an extra derivative circuitry exists. The whole circuit has been simulated using LTSpice and the results had demonstrated the circuit capability to operate as an impulse generator. The Gaussian impulse achieves a very small pulse width of about 192ps, and amplitude of 44mVpp, with power dissipation of 1μW. The complete circuit occupies area of 220×220 μm2 including the inductor, but without PADS.
asia-pacific microwave conference | 2014
Luiz Carlos Moreira; Jose Fontebasso Neto; Wilhelmus A. M. Van Noije; Emmanuel Torres Rios
Archive | 2017
Ricardo Kenji Oi; Jose Fontebasso Neto; Caio Cesar Maia; Debora Agraz Cutino Nogueira; Renato Fares Khalil
Exacta | 2016
Anderson Willian Souza; Daniel Barzan de Matos Amaral; Ricardo Kenji Oi; João Batista Carneiro; Jose Fontebasso Neto