Luiz Carlos Moreira

A CMOS UWB pulse beamforming transmitter with Vivaldi array antenna for vital signals monitoring applications

This paper presents a new beamforming transmitter, Ultra Wide Band (UWB) pulse generator for contactless radar monitoring applications of vital signals. The system consists of a programmable delay circuit (PDC or τ), UWB pulse generator circuit and an array of Vivaldi planar antennas. Also, a new CMOS PDC controller is developed in order to provide pulse beamforming. The circuit was designed using 0.18μm CMOS process and the planar antenna array was designed with copper and FR-4 substrate. Spice circuit simulations show the generation of pulses with 136mVpp amplitudes and 350ps width. The generated pulse spectrum complies with the Federal Communications Commission (FCC) spectrum mask in the 6-10GHz range. The dynamic energy consumption is around 0.4pJ per pulse using 2V power supply at pulse repetition rate (PRR) of 100MHz. Electromagnetic simulations using CST MW 2010 shows the Main Lobe with an average magnitude of 12dBi, 30° × 32° angular width, and a beam steering between -15° and +25° for θ, and between -20° and +20° for the φ angles. This system can be applied to human monitoring in hospitals, ports and airports, industrial plants - like refineries and oil platforms - and military units as well.

A 2 nd derivative Gaussian UWB pulse transmitter design using a cross inductor

This paper presents a UWB pulse transmitter design using MOSIS/IBM 0.35µm CMOS process. A 2nd order derivative Gaussian pulse is generated using a Phase Detector (PD), which consists of a D-Latch with an effective phase difference of 46ps, and at the output an extra derivative circuitry exists. It generates pulses of 100ps width. The Gaussian impulse achieves a very small pulse width of about 200ps, and amplitude of 120mVpp. The complete circuit occupies a very small area of 63.4×42.4µm2 without the PADs and inductor. The Sonnet tools were used to simulate and evaluate the performance of the novel cross inductor structure. In order to make a fair comparison, the new structure and conventional rectangular inductor were designed to get similar inductance value, and with the same segment width and spacing fixed at 10 µm. The result shows the feasibility to use the cross structure with an area of 160×140µm2, while the square planar inductor would occupy an area of 180×180µm2. Thus, the last one needs 45% more area than the cross inductor, so this cross inductor leads to an extra reduction in Silicon area, what is one of the main purposes of this work to get a small UWB transmitter. The compact shaper circuit and cross inductor has lead to the whole circuit area of only 0.0283mm2 (about 20% of other published works).

Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology

This paper describes the design, and experimental characterization of cross inductors in a 0.35μm CMOS technology. The Sonnet tools were used to simulate and evaluate the performance of the new inductor structure, whose core has perpendicular crossed segments at the two highest layers available of the technology. Due to this arrangement, the positive as well as the negative mutual inductance are almost null. To make a fair comparison, the new structure and conventional rectangular inductor were designed to get similar inductance value, and with the same segment width and spacing fixed at 10μm. The proposed cross structure occupied an area of 160x140μm2 while the square planar inductor presents an area of 180x180μm2. Thus, the last one occupies 45% more area than the cross inductor. Some deembedding structures were fabricated and used to subtract the effect of the test-fixture in the on-wafer measurements. The main experimental results are: for cross inductor an inductance value of 2.1nH and Q of 3.3 at 5.2GHz and for the square one an inductance of 1.9nH and Q of 5.5 at 5.5GHz. Although, for similar inductance value, the quality factor of the cross inductor is lower than for the rectangular inductor one, the new cross inductor structure shows to be useful at RF circuits where the inductors are largely used and the most area consuming components.

Small area cross type integrated inductor in CMOS Technology

This paper describes the design and simulation, using the SONNET tool, of a new inductor structure with crossed segments (cross). In order to compare, the new and conventional rectangular inductors were designed using a 0.35 mum CMOS technology. To make a fair comparison we fixed the segment width and spacing to 10 mum. After the design, the cross inductor presents an area of 120times140 mum2, an inductance of 1.75 nH and Q of 4.1 at 8 GHz, while the square planar inductor presents an area of 180times180 mum2, an inductance of 1.65 nH and Q of 5.5 at 8 GHz. Thus, the square inductor occupies 92% more area than the cross inductor.

Systematic modeling and parameter extraction for on-chip inductors in CMOS technology

This paper presents a systematic methodology for characterizing and modeling on-chip inductors over a lossy substrate directly from S-parameter measurements. The model implementation neither requires precise knowledge of geometry or fabrication process. This eases the representation of inductors in SPICE-like simulators at high frequencies. Excellent model-experiment correlation is achieved up to 12 GHz for the circuit network parameters as well as for the Q-factor.

Inductorless very small 4.6pJ/pulse 7th derivative pulse generator for IR-UWB

This paper presents a fully integrated low-power 7th derivative Gaussian pulse generator for UWB applications designed in 180 nm CMOS technology. We propose a simple architecture based on parallel pulse generator blocks that produce Gaussian pulses, and a pulse shaping stage which adjusts each pulse amplitude individually. The whole circuit has been simulated and the results have demonstrated the circuit capability to operate like an impulse generator. The implemented circuit generates pulse envelopes of 944 ps width and maximum amplitude of 120 mVpp, an average power of 3.8 mW/pulse at 100 MHz PRF and about energy of 4.6 pJ/pulse. The circuit does not need any inductor leading to a very small area; therefore, the complete circuit occupies only 73×75 μm2 (without PADs). This pulse generator complies with FCC UWB spectral power mask.

A pulse generator UWB-Ultra Wide Band using PFD Phase Frequency Detector in 180nm CMOS technology

This paper presents a design of a transmitter pulse generator UWB-Ultra Wide Band in standard 180 nm MOSIS/CMOS technology. We proposed a pulse generator using Phase-Frequency Detector (PFD) that is designed using a modified architecture TSPC (True Single-phase Clock) positive edge triggered D Latch. The operation range and power consumption PFD is 45 ¿W to 2 mW, from 200 MHz to 5 GHz, respectively, and a minimum phase difference is 30 ps. Whole circuit has been simulated using LTSpice and the results had demonstrated the circuit capability to operate as an impulse generator. It generates pulses with 70 ps width. The Gaussian impulse achieves a very short pulse width of 133 ps, and amplitude of 48 mV. The generated pulse shape is similar to the 1st derivative. The complete design, occupies an area of 35400 ¿m2 including the inductor and without the PAD`s and a power consumption of 2 mW at 2.56 GHz@ 2 V supply voltage.

A design of a BPSK transmitter front end for ultra-wideband in 130nm CMOS

This paper presents a fully integrated BPSK (Binary Phase Shift Keying) Transmitter Front End for Ultra-Wideband (UWB) applications, designed in 130 nm CMOS technology. A simple architecture based on parallel pulse generator blocks in parallel is proposed to produce 9th derivative Gaussian pulses. In addition to the pulse generator, the circuit comprises a passive balun circuit, a common source amplifier, and a BPSK modulator. The transmitter has been simulated and the results demonstrated the circuit capability to operate as a front end BPSK transmitter. The proposed circuit generates output pulse envelopes of width 0.8 ns and maximum amplitude of 40 mVpp, an average power consumption of 1.9 μW/pulse and energy of 1.6 fJ/pulse when fed with a 715 MHz clock and 100 MHz data sources. The whole circuit occupies 480 × 320 μm2 (without pads). This pulse generator complies with FCC UWB spectral power mask).

All-digital reconfigurable IR-UWB pulse generator using BPSK modulation in 130nm RF-CMOS process

A new circuit technique, the reconfigurable puise generator circuit is proposed to produce a puise width inversely proportional to the spectrum power bandwidth in the Impulse Radio Ultra-Wide Band (IR-UWB) circuits. The complete circuit was based on two pulse generator blocks using Positive Pulse Generator (PPG), and Negative Pulse Generator (NPG) to compose a rectangular waveform at the output. These pulse generators have been implemented with high impedance circuits and are selected by digital control signals. Thus, each block can be adjusted to generate up to eight sequential pulses per clock edge. The circuit was designed to use Binary Phase Shift Keying (BPSK) scheme for modulation and can change the frequency spectrum of the signal pulses. In addition, we implemented a voltage divider circuit using two transistors in parallel with a charge pump circuit to control the signal amplitude at the output. The proposed pulse generator circuit operates at a maximum operation frequency at 12 GHz. The pos-layout simulations were performed using LTSpice, and the results show a pulse amplitude of 160mV and an average power consumption of 11.3 fJ per pulse at lowest operating frequency and 85.3 fJ per pulse at highest operating frequency, for a Pulse Repetition Frequency (PRF) of 100MHz at 1.3V power supply voltage. The core chip size occupies a very small area of 210 μm × 75 μm (without PADs).

An equivalent electrical circuit model for spiral and cross inductors on 0.35 µm CMOS technology

This paper presents a simple equivalent electrical circuit model to represent spiral and cross inductors on CMOS Technology. The inductors were designed and simulated using Momentum/ADS from Keysight, and were fabricated on AMS 0.35 µm CMOS technology. Simulation data was used to develop a RLC model for the inductors, where the reactive elements are constant and the resistance depends on frequency. A linear equation was proposed to represent the frequency dependence of the inductors resistance. The simulated results of spiral and cross inductors were in good agreement with the model results. On chip measurements of the inductors were performed from 1 to 10 GHz using a network analyzer. The inductance and maximum quality factor obtained from the measured data were well predicted by the proposed model, which showed good precision on spite of its simplicity.