Wilhelmus A. M. Van Noije

A CMOS UWB pulse beamforming transmitter with Vivaldi array antenna for vital signals monitoring applications

This paper presents a new beamforming transmitter, Ultra Wide Band (UWB) pulse generator for contactless radar monitoring applications of vital signals. The system consists of a programmable delay circuit (PDC or τ), UWB pulse generator circuit and an array of Vivaldi planar antennas. Also, a new CMOS PDC controller is developed in order to provide pulse beamforming. The circuit was designed using 0.18μm CMOS process and the planar antenna array was designed with copper and FR-4 substrate. Spice circuit simulations show the generation of pulses with 136mVpp amplitudes and 350ps width. The generated pulse spectrum complies with the Federal Communications Commission (FCC) spectrum mask in the 6-10GHz range. The dynamic energy consumption is around 0.4pJ per pulse using 2V power supply at pulse repetition rate (PRR) of 100MHz. Electromagnetic simulations using CST MW 2010 shows the Main Lobe with an average magnitude of 12dBi, 30° × 32° angular width, and a beam steering between -15° and +25° for θ, and between -20° and +20° for the φ angles. This system can be applied to human monitoring in hospitals, ports and airports, industrial plants - like refineries and oil platforms - and military units as well.

A 2 nd derivative Gaussian UWB pulse transmitter design using a cross inductor

This paper presents a UWB pulse transmitter design using MOSIS/IBM 0.35µm CMOS process. A 2nd order derivative Gaussian pulse is generated using a Phase Detector (PD), which consists of a D-Latch with an effective phase difference of 46ps, and at the output an extra derivative circuitry exists. It generates pulses of 100ps width. The Gaussian impulse achieves a very small pulse width of about 200ps, and amplitude of 120mVpp. The complete circuit occupies a very small area of 63.4×42.4µm2 without the PADs and inductor. The Sonnet tools were used to simulate and evaluate the performance of the novel cross inductor structure. In order to make a fair comparison, the new structure and conventional rectangular inductor were designed to get similar inductance value, and with the same segment width and spacing fixed at 10 µm. The result shows the feasibility to use the cross structure with an area of 160×140µm2, while the square planar inductor would occupy an area of 180×180µm2. Thus, the last one needs 45% more area than the cross inductor, so this cross inductor leads to an extra reduction in Silicon area, what is one of the main purposes of this work to get a small UWB transmitter. The compact shaper circuit and cross inductor has lead to the whole circuit area of only 0.0283mm2 (about 20% of other published works).

An optimization-based reconfigurable design for a 6-bit 11-MHz parallel pipeline ADC with double-sampling S&H

This paper presents a 6 bit, 11MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 µm AMS technology, and some postlayout results are shown.

2.45GHz low phase noise LC VCO design using Flip Chip on low cost CMOS technology

Phase Noise performance of LC VCOs is strongly dependent on the Quality Factor of the Inductors. As known, low cost CMOS technologies, the on-chip inductors have low quality factors compared to external inductors. But, using external inductors connected by traditional bonding technologies limits the integration capacity. To implement high performance RF circuits, the use of the Flip Chip technology is growing in ICs packaging. This work presents a comparison between two LC VCOs operating at 2.4GHz ISM band, using a standard 0.35μm CMOS process. One using internal inductor (OC-VCO), and a second using a high-Q external inductor connected by Flip Chip Technology (FC-VCO). The results for the designed FC-VCO are a low phase noise of -121dBc/Hz@1MHz and -132dBc/Hz@3MHz, tuning range of 203MHz and power consumption of 10.8mW at 3V. FC-VCO improves -9.7dBc/Hz@1MHz if compared with the OC-VCO using the same power consumption and inductance value. Additionally, FC-VCO presents a better figure of merit (FOM) than other published works, even for more advanced technologies.

Analog design synthesis method using simulated annealing and particle swarm optimization

This paper presents a method for analog design synthesis at circuit-level and pareto front exploration of the design through a combined approach of Simulated Annealing (SA) and Particle Swarm Optimization (PSO). The method consists of dividing the design parameters search in three main parts. The first has the objective of finding the minimal specifications defined by the user through the use of SA and using an aggregate objective function to combine all the design objectives into a single cost function. The second part starts when all the minimal specs are met and it performs a single-objective optimization for each objective in order to obtain a non-exhaustive exploration of the pareto front. The third part applies PSO for multiple objective in order to spread the results and find a more accurate pareto front of the design. This approach allows the designer to have a visual feedback about the trade-offs of the design to a specific topology and technology selection. Results of a folded-cascode opamp circuit-level synthesis using a 0.35 μm technology show this method provides a fast approach to good solutions using SA (considering Gain, UGF, Slew Rate, Consumption, Phase Margin, ICMR, Output Swing and PSRR specifications) and further good pareto front exploration through its connection with the PSO algorithm.

Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology

This paper describes the design, and experimental characterization of cross inductors in a 0.35μm CMOS technology. The Sonnet tools were used to simulate and evaluate the performance of the new inductor structure, whose core has perpendicular crossed segments at the two highest layers available of the technology. Due to this arrangement, the positive as well as the negative mutual inductance are almost null. To make a fair comparison, the new structure and conventional rectangular inductor were designed to get similar inductance value, and with the same segment width and spacing fixed at 10μm. The proposed cross structure occupied an area of 160x140μm2 while the square planar inductor presents an area of 180x180μm2. Thus, the last one occupies 45% more area than the cross inductor. Some deembedding structures were fabricated and used to subtract the effect of the test-fixture in the on-wafer measurements. The main experimental results are: for cross inductor an inductance value of 2.1nH and Q of 3.3 at 5.2GHz and for the square one an inductance of 1.9nH and Q of 5.5 at 5.5GHz. Although, for similar inductance value, the quality factor of the cross inductor is lower than for the rectangular inductor one, the new cross inductor structure shows to be useful at RF circuits where the inductors are largely used and the most area consuming components.

A 2.7ua sub1-v voltage reference

A simplified voltage reference topology with low power consumption based on MOS transistors in weak inversion operation is presented. A 176 <i>mV</i> @ 27°<i>C</i> output voltage with a quiescent current of 2.7 μ<i>A</i> @ 3.3 <i>V</i> and a thermal coefficient of 8.8 μ<i>V/°C</i> in the temperature range of [-25; 100] °<i>C</i> had been achieved in measurement results. The circuit had been fabricated in AMS 0.35 μm C35B4 CMOS technology with an active area of 105 & <μμm x 212 μm.

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter

This paper presents a small area CMOS current-steering segmented digital-to-analog converter (DAC) design used in a RF transmitter stage for 2.45GHz Bluetooth applications. The current source design strategy is based on an iterative scheme which variables are adjusted by a simple way, satisfying the requirements, minimizing power consumption and reaching the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy of small area consumption for the current-steering DAC design is included. The DAC was designed and implemented in 0.35mm 4M2P CMOS technolyogy. Some performance results obtained through experimental test are: chip active area of only 200mm-200mm, full scale output current of 700mA at 3.3V power supply, INL=0.3LSB, DNL=0.37LSB, SFDR=58dB for output sine wave frequency of Fout = 1MHz and Fs = 50MHz sampling frequency, SFDR=52dB for Fout = 1MHz and Fs = 10MHz.

Configurable low noise readout front-end for gaseous detectors in 130nm CMOS technology

A noise improved Charge Sensitive Amplifier (CSA) topology for a gaseous detector readout front-ends is presented. The proposed topology is based on the traditional cascode topology with addition of a PMOS to partially cancel the channel thermal noise and the flicker noise of the CSA input transistor. A noise improvement of about 23% was obtained without increasing power consumption. Additionally, the proposed circuit reduces the dependence of the noise on the detector capacitance. A chip with 5 front-ends channel implemented with the proposed CSA topology and a Semi-Gaussian shaper of 4th order was designed in TSMC 130nm CMOS technology. The fabricated front-end was designed for 160ns of peaking time, sensitivity of 30mV/fC and Equivalent Noise Charge (ENC) of 428e. The measured power consumption of the CSA and of the pulse shaper were 3.3mW and 4.2mW, respectively.

Inductorless very small 4.6pJ/pulse 7th derivative pulse generator for IR-UWB

This paper presents a fully integrated low-power 7th derivative Gaussian pulse generator for UWB applications designed in 180 nm CMOS technology. We propose a simple architecture based on parallel pulse generator blocks that produce Gaussian pulses, and a pulse shaping stage which adjusts each pulse amplitude individually. The whole circuit has been simulated and the results have demonstrated the circuit capability to operate like an impulse generator. The implemented circuit generates pulse envelopes of 944 ps width and maximum amplitude of 120 mVpp, an average power of 3.8 mW/pulse at 100 MHz PRF and about energy of 4.6 pJ/pulse. The circuit does not need any inductor leading to a very small area; therefore, the complete circuit occupies only 73×75 μm2 (without PADs). This pulse generator complies with FCC UWB spectral power mask.