José Francisco López

Analysis of fast block matching motion estimation algorithms for video super-resolution systems

In general, all the video super-resolution (SR) algorithms present the important drawback of a very high computational load, mainly due to the huge amount of operations executed by the motion estimation (ME) stage. Commonly, there is a trade-off between the accuracy of the estimated motion, given as a motion vector (MV), and the computational cost associated. In this sense, the ME algorithms that explore more exhaustively the search area among images use to deliver better MVs, at the cost of a higher computational load and resources use. Due to this reason, the proper choice of a ME algorithm is a key factor not only to reach real-time applications, but also to obtain high quality video sequences independently of their characteristics. Under the hardware point of view, the preferred ME algorithms are based on matching fixed-size blocks in different frames. In this paper, a comparison of nine of the most representative Fast Block Matching Algorithms (FBMAs) is made in order to select the one which presents the best tradeoff between video quality and computational cost, thus allowing reliable real-time hardware implementations of video super-resolution systems.

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

A Low-Computational-Complexity Algorithm for Hyperspectral Endmember Extraction: Modified Vertex Component Analysis

Endmember extraction represents one of the most challenging aspects of hyperspectral image processing. In this letter, a new algorithm for endmember extraction, named modified vertex component analysis (MVCA), is presented. This new technique outperforms the popular vertex component analysis (VCA) by applying a low-complexity orthogonalization method and by utilizing integer instead of floating-point arithmetic when dealing with hyperspectral data. The feasibility of this technique is demonstrated by comparing its performance with VCA on synthetic mixtures as well as on the well-known Cuprite hyperspectral image. MVCA shows promising results in terms of much lower computational complexity, still reproducing similar endmember accuracy than its original counterpart. Moreover, the features of this algorithm combined with state-of-the-art hardware implementations qualify MVCA as a good potential candidate for all those applications in which real time is a must.

Mapping control-intensive video kernels onto a coarse-grain reconfigurable architecture: the H.264/AVC deblocking filter

Deblocking filtering represents one of the most compute intensive tasks in an H.264/AVC standard video decoder due to its demanding memory accesses and irregular data flow. For these reasons, an efficient implementation poses big challenges, especially for programmable platforms. In this sense, the mapping of this decoders functionality onto a C-programmable coarse-grained reconfigurable architecture named ADRES (architecture for dynamically reconfigurable embedded systems) is presented in this paper, including results from the evaluation of different topologies. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the filtering as well as an increase in the degree of instruction parallelism (ILP) when compared with an implementation on a very long instruction word (VLIW) dedicated processor. This demonstrates that high ILP is achievable on the ADRES even for irregular, data-dependent kernels

A New Preprocessing Technique for Fast Hyperspectral Endmember Extraction

Hyperspectral image processing represents a valuable tool for remote sensing of the Earth. This fact has led to the inclusion of hyperspectral sensors in different airborne and satellite missions for Earth observation. However, one of the main drawbacks encountered when dealing with hyperspectral images is the huge amount of data to be processed, in particular, when advanced analysis techniques such as spectral unmixing are used. The main contribution of this letter is the introduction of a novel preprocessing (PP) module, called SE2PP, which is based on the integration of spatial and spectral information. The proposed approach can be combined with existing algorithms for endmember extraction, reducing the computational complexity of those algorithms while providing similar figures of accuracy. The key idea behind SE2PP is to identify and select a reduced set of pixels in the hyperspectral image, so that there is no need to process a large amount of them to get accurate spectral unmixing results. Compared to previous approaches based on similar spatial and spatial-spectral PP strategies, SE2PP clearly outperforms their results in terms of accuracy and computation speed, as it is demonstrated with artificial and real hyperspectral images.

Low cost efficient architecture for H.264 motion estimation

A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the power dissipation. As result, the implementation of the architecture in a low cost commercial FPGA is outlined in this paper, showing characteristics such as a reduced area occupation and an appropriate range of operation frequencies that make the architecture suitable for portable multimedia devices.

A novel real-time DSP-based video super-resolution system

The possibility of increasing the spatial resolution of video sequences is becoming extremely important in present-day multimedia systems. In this sense, super-resolution represents a smart way to obtain high-resolution video sequences from a finite set of low-resolution video frames. This set of low-resolution images must be obtained under different capture conditions of the image, from different spatial positions and/or from different cameras - this being the super-resolution paradigm, which is one of the fundamental challenges of sensor fusion. However, the vast computational cost associated with common super-resolution techniques jeopardizes their usefulness for real-time consumer applications. To alleviate this drawback, an implementation of a proprietary super-resolution algorithm mapped onto a hardware platform based on a digital signal processor (DSP) is presented in this paper. The results obtained show that, after an incremental optimization procedure, we are able to obtain super-resolved CIF video sequences (352 × 288 pixels) at 38 frames per second.

Low-cost super-resolution algorithms implementation over a HW/SW video compression platform

Two approaches are presented in this paper to improve the quality of digital images over the sensor resolution using super-resolution techniques: iterative super-resolution (ISR) and noniterative super-resolution (NISR) algorithms. The results show important improvements in the image quality, assuming that sufficient sample data and a reasonable amount of aliasing are available at the input images. These super-resolution algorithms have been implemented over a codesign video compression platform developed by Philips Research, performing minimal changes on the overall hardware architecture. In this way, a novel and feasible low-cost implementation has been obtained by using the resources encountered in a generic hybrid video encoder. Although a specific video codec platform has been used, the methodology presented in this paper is easily extendable to any other video encoder architectures. Finally a comparison in terms of memory, computational load, and image quality for both algorithms, as well as some general statements about the final impact of the sampling process on the quality of the super-resolved (SR) image, are also presented.

Low depth carry lookahead addition using charge recycling threshold logic

The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. Two such adders are designed using the recently proposed charge recycling threshold logic gate. The adders are shown to have a very low logic depth, and significantly reduced area and power dissipation compared to other dynamic CMOS implementations.

A high quality/low computational cost technique for block matching motion estimation [video coding applications]

Motion estimation is the most critical process in video coding systems. First of all, it has a definitive impact on the rate-distortion performance given by the video encoder. Secondly, it is the most computationally intensive process within the encoding loop. For these reasons, the design of high-performance low-cost motion estimators is a crucial task in the video compression field. An adaptive cost block matching (ACBM) motion estimation technique is presented in this paper, featuring an excellent tradeoff between the quality of the reconstructed video sequences and the computational effort. Simulation results demonstrate that the ACBM algorithm achieves a slightly better rate-distortion performance than the one given by the well-known full search algorithm block matching algorithm with reductions of up to 95% in the computational load.