V. de Armas

An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented. The deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both the encoding and decoding processes. The proposed architecture is based on a double- filter strategy that results in a significant saving in filtering cycles, memory requirements and gate count when compared with state-of-the-art approaches. The proposed architecture is implemented in synthesizable HDL at RTL level and verified with the reference software. This hardware is designed to be used as part of a complete H.264/A VC video coding system.

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

Low cost efficient architecture for H.264 motion estimation

A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the power dissipation. As result, the implementation of the architecture in a low cost commercial FPGA is outlined in this paper, showing characteristics such as a reduced area occupation and an appropriate range of operation frequencies that make the architecture suitable for portable multimedia devices.

Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches

Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ scheduling algorithms, as exemplified by PIM and iSLIP, re based on parallel and iterative request-grant-accept arbitration schemes. Conventional performance evaluation of these scheduling algorithms, does not consider the effect of some issues inherent to their implementation on a modular and scalable VOQ switch with input ports and switch matrix residing on separate cards. One of the main issues is the Round-Trip Delay (RTD), defined as the latency between a connection is requested to the switch matrix card and the associated acceptance notification is received on the input port card. In this paper, the effect of RTD on performance parameters for PIM and iSLIP algorithms is presented, not being considered in deep in previous works appearing In the literature. Based on simulation results, RTD is demonstrated to affect significantly contention on output ports and mean queuing delay, and thus degrade the performance of cell-based VOQ switches.

A cell and macrocell compiler for GaAs VLSI full-custom design

A gallium arsenide automated layout generation system (OLYMPO) for SSI, MSI and LSI circuits used in GaAs VLSI design has been developed. We introduce a full-custom layout style, called RN-based cell model, that it is suited to generate low self-inductance circuit layouts of cells and macrocells. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator. Experimental results demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.

Experimental gigabit multidrop serial backplane for high speed digital systems

Maximum data rate in todays available multidrop backplanes is limited to 400 Mbps due to signal integrity concerns. In this paper, an experimental gigabit multidrop serial backplane for high-speed digital systems based on a novel asymmetrical broadband power splitter configuration with matching trace impedance, is presented. Experimental results obtained from constructed prototype demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data transfer rate of 3 Gbps.

High speed GaAs subsystem design using feed through logic

In this paper design of fast arithmetic circuits using a GaAs based feed through logic (FTL) family is presented. A modified version of FTL termed differential FTL (DFTL) is introduced and basic aspects of design methodologies using FTL are discussed. A 4-bit ripple-carry adder is designed and its performance is evaluated against other similar reported works in terms of device count, chip area, delay clock rate, and power consumption. It is shown how arithmetic circuits based on FTL outperform the evaluated performance. A 4-bit magnitude comparator is designed and performance evaluated against four cascaded 1-bit comparators.

GMDS: hardware implementation of novel real output queuing architecture

In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose line card which includes a Virtex-II 6000 FPGA. This switch is named GMDS (gigabit multidrop switch) and its main features are the switch matrix replacement by the multidrop backplane -increasing system reliability-, variable length packet switching support -avoiding bandwidth efficient loss-, multiple output queuing structure for supporting QoS (quality of service) and a minimum speedup.

Variable length packet scheduler algorithm with QoS support

A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and simulated in C++ language under uniform and bursty traffic conditions.

A quarter pixel precision motion estimation architecture for H.264/AVC video coding

H.264/AVC is the most recent and promising international video coding standard developed by the ITU-T Video Coding Experts Group in conjunction with the ISO/IEC Moving Picture Experts Group. This standard has been designed in order to provide improved coding efficiency and network adaptation. In this sense, H.264/AVC provides superior features when compared with its ancestors such as MPEG-2, MPEG-4 and H.263 but at the expenses of a prohibitive computational cost for real time applications. In particular, the motion estimation results to be the most intensive task in the whole encoding process, and for this reason, efficient architectures as the one presented in this paper to compute the 41 motion vectors per macroblock required by the H.264/AVC video coding standard, are needed in order to meet real conditions. This paper deals with a low cost VLSI architecture capable to obtain half and quarter pixel precision motion vectors, applying the correspondent techniques in order to obtain these motion vectors as demanded by the H.264/AVC standard. Techniques such as the reuse of the results obtained for smaller blocks and the possibility of avoiding the use of certain motion estimation modes have been introduced in order to obtain a flexible low-power hardware solution. As a result, the proposed architecture has been synthesized and generated to a commercial FPGA device, producing a fully functional embedded prototype capable of processing up to QCIF images at 30 fps with low area occupation.