José Pineda de Gyvez

Standard cell sizing for subthreshold operation

Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs

A time-domain methodology for statistical simulation of nonlinear dynamic integrated circuits with arbitrary excitations is presented. The statistical behavior of the circuits is described as a set of stochastic differential equations rather than estimated by a population of realizations and Gaussian closure approximations are introduced to obtain a closed form of moment equations. Statistical simulation of specific circuits shows that the proposed numerical methods offer accurate and efficient solution of stochastic differentials for variability and noise analysis of integrated circuits.

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller

It has been demonstrated that dynamic voltage and frequency scaling (DVFS) leads to a considerable saving in dynamic and static power of a processor. In this paper, we present an adaptive framework that can be used to dynamically adjust supply voltage and frequency of a processor under different application workloads. Voltage scaling decisions are made by a fuzzy logic (FL) block based on variations of the processors workload. By observing the supply-current of the processor and also its variation rate, the FL block can drive the processor to operate at the lowest possible voltage and also the corresponding minimum frequency, in which a specific application can meet all of its deadlines under time-constrained operation. As the voltage can change at the same time as the workload varies, significant savings in both dynamic and static power are achieved. Simulation results show that our approach outperforms a PID controller under distinct working loads.

Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning

In this chapter, we concentrate on technological quantitative pointers for adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in modem CMOS digital designs. In particular, we will present the power savings that can be expected, the power-delay trade-offs that can be made, and the implications of these techniques on present semiconductor technologies. Furthermore, we will show to which extent process-dependent performance compensation can be used. Our presentation is a result of extensive analyses based on test-circuits fabricated in the state-of-the-art CMOS processes. Experimental results have been obtained for both 9Onm and 65nm CMOS technology nodes.

Subband coding and image compression using CNN

The cellular neural network paradigm has found many applications in image processing. However, algorithms for image compression using CNN have scarcely been explored. CNN programmability is based on a new algorithmic style based on the spatio-temporal properties of the array. By exploiting the massive parallelism provided by CNN and the convolutional key basic instruction, a fast and efficient compression process can be achieved. This paper presents new templates and low-complexity algorithms to perform both the linear and non-linear operations needed for image compression. In this work, we have addressed all the transformation steps needed in image compression, i.e. decorrelation, bit allocation, quantization and bit extraction. From all possible compression techniques the wavelet subband coding was chosen because it is considered one of the most successful techniques for lossy compression. It allows a high compression ratio while preserving the image quality. All these advantages are implemented in the algorithms hereby presented.

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage

Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. The main drawbacks are performance degradation due to the exponentially reduced driving current, and the effect of increased sensitivity to process variation. To obtain energy savings while reducing performance degradation, we propose the design of a robust sub-threshold library and post-silicon tuning using an adaptive fuzzy logic controller which performs body bias scaling. We show that our methodology is able to fix the performance, consequently, making the system more energy efficient and achieving maximum yield.

Extending Amdahl's law for energy-efficiency

This paper presents a study about the potential dynamic energy improvement that can be achieved when hardware parallelization is used to increase the energy efficiency of the system rather than to increase performance. We show that it is possible, at early design stages, to know the number of parallel cores that allows a system to achieve the maximum energy improvement for a given throughput. Using Amdahls law to represent the ratio between the serial and parallel portion of an application, we can derive simple formulas to obtain the optimum frequency, supply voltage and energy improvement while the execution time remains constant.

Time-multiplexing scheme for cellular neural networks based image processing

The state of the art work in Cellular Neural Networks (CNN) has concentrated on VLSI implementations without really addressing the ‘systems level’. While efficient implementations have been reported, no reports have been presented on the use of these implementations for processing large complex images. The work hereby presented introduces a strategy to process large images using small CNN arrays. The approach,time-multiplexing, is prompted by the need to simulate hardware models and test hardware implementations of CNN. For practical size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware processors and all the pixels in the image involved. This paper presents a practical solution by processing the input image block by block, with the number of pixels in a block being the same as the number of CNN processors in the hardware. The algorithm for implementing this approach is also presented, along with image processing results obtained from an actual laboratory discrete hardware prototype.

Nonlinear computability based on chaos

Two new computing models based on information coding and chaotic dynamical systems are presented. The novelty of these models lies on the blending of chaos theory and information coding to solve complex combinatorial problems. A unique feature of our computing models is that despite the nonpredictability property of chaos, it is possible to solve any combinatorial problem in a systematic way, and with only one dynamical system. This is in sharp contrast to methods based on heuristics employing an array of chaotic cells. To prove the computing power and versatility of our models, we address the systematic solution of classical NP-complete problems such as the three colorability and the directed Hamiltonian path in addition to a new chaotic simulated annealing scheme.

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation

Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5% performance loss.