Amir Zjajo

BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits

This paper reports a new built-in self-test scheme for analog and mixed-signal devices based on die-level process monitoring. The objective of this test is not to replace traditional specification-based tests, but to provide a reliable method for early identification of excessive process parameter variations in production tests that allows quickly discarding of the faulty circuits. Additionally, the possibility of on-chip process deviation monitoring provides valuable information, which is used to guide the test and to allow the estimation of selected performance figures. The information obtained through guiding and monitoring process variations is re-used and supplement the circuit calibration

Power-scan chain: design for analog testability

This paper reports a design for testability technique, which provides necessary diagnostic capability for signature-based testing of analog circuits. To facilitate this kind of testing, it is preferable to observe the current (or voltage) signatures of individual cores instead of observing the current (or voltage) signature of the whole analog SoC. Therefore, our DfT works like a power-scan chain aimed at turning on/off analog cores in an individual manner, providing an observability means at the cores power and output terminals, and at exciting the core under test. The proposed DfT can be used for engineering pre-characterization as well, and can easily be interfaced to standards like I2C and IEEE 1149.1 TAP controllers. In this paper, we further provide experimental evidence of our approach as applied to an RF device

Evaluation of signature-based testing of RF/analog circuits

Due to its low cost, low test time and reduced test complexity, structural testing is preferred to functional whenever possible. The study presented in this paper indicates that the two low-frequency structural test methods considered, power supply current monitoring and the power supply ramping technique, provide a valuable supplement/alternative when one of the functional tests (gain, noise figure and total harmonic distortion) in the test set can be complemented or substituted by structural test and add to or maintain no loss of fault coverage.

Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits

A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit’s DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty behavior. A systematic method is proposed for the fault discrimination to minimize the probability that the circuit is accepted as a fault-free when it is faulty. Tests are generated and evaluated taking into account the potential fault masking effects of process spread on the faulty circuit responses. The introduced fault model is validated on a time-interleaved sample-and-hold circuit. Simulation results demonstrate the effectiveness of the model.

Calibration and Debugging of Multi-step Analog to Digital Converters

This paper reports a new approach for debugging of the analog to digital converters based on process monitoring and extended design-for-test implementation. The circuit is re-configured in such a way that all sub-blocks are analysed and tested for their full input range allowing full observability and controllability of the analog to digital converter. To set initial data, estimate the parameter update and to guide the test, dedicated monitors have been designed. Additionally, the second presented algorithm allow circuit calibration without explicit need for any dedicated test signal nor requires a part of the conversion time. It works continuously and with every signal applied to the ADC.