Josef Hausner

SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency

A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.

Unique word based phase tracking algorithms for SC/FDE-systems

In this paper we consider phase tracking algorithms for single carrier systems with frequency domain equalizers (SC/FDE), which make use of the concept of unique word (UW) blockwise extension instead of the classical concept of cyclic prefix (CP) like it is used for example in OFDM (orthogonal frequency division multiplexing). Very similar to IEEE 802.11a like OFDM systems the overall baseband processing performance of SC/FDE systems largely depends on the design of channel estimation and synchronization algorithms. Some of the synchronization tasks are very straight forward, but the algorithm developer has a lot of freedom for the design of the channel estimator, and for the design of the residual carrier frequency offset tracking procedure (which we call phase tracking). In this paper we focus on the design and performance of unique word based phase tracking algorithms, which are being compared with pilot carrier based phase tracking algorithms for IEEE 802.11a like OFDM systems.

High Precision Radar Distance Measurements in Overmoded Circular Waveguides

Distance measurements in overmoded waveguides are an important application for industrial radar systems. The accuracy of the measurements is deteriorated by the appearance of higher order modes in the metal tube, although the frequency-modulated continuous-wave method is used with a large bandwidth. This paper describes the problems caused by dispersion and multimode propagation and presents a solution in the form of mode-matched antennas for feeding the overmoded waveguide. It is shown that different modes, e.g., the H11 and H01 modes, are equally well suited for precision distance measurements, as is demonstrated both by simulations and measurements.

Acceleration of the L4/Fiasco microkernel using scratchpad memory

In this paper we analyze the potential of using scratchpad memory in embedded devices to accelerate the operation of the L4/Fiasco microkernel affecting basically all applications on top of the kernel including virtualization software. We examine several low-level L4 system calls using a virtual prototype of Infineons S-GOLD® platform for mobile phones based on an ARM11 processor. We present a profiling strategy identifying critical parts of the microkernel to be placed on the scratchpad memory. Applying this approach we achieve a worstcase speedup of up to 29% with one page of scratchpad memory (4 kB) and up to 63% with two pages. With regard to the real-time capability of Fiasco, worst-case interrupt latency can be improved by almost 45% with only 4 kB of scratchpad memory.

On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals

In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data plane processing of the LTE protocol stack layer 2 (L2) in downlink direction. For this purpose, a hybrid design approach is adopted allowing first investigations of future mobile phone platforms on the system level (using virtual prototyping) combined with more accurate power-area explorations of hardware accelerators on the architectural level. Additionally, we show the employment of an LTE data generator peripheral, realizing L2 uplink processing and thus enabling platform analyses in a closed virtual environment. Furthermore, a modeling technique for a fast and efficient design of virtual hardware accelerator peripherals is demonstrated. A reasonable hardware/software partitioning can thereby be achieved early in the design phase. Once the system architecture is settled and thus the solution space is reduced, VHDL models of the accelerators are developed in order to find a suitable hardware implementation for LTE terminals based on timing constraints by system level simulations. As a case study, the LTE ciphering scheme, including the Advanced Encryption Standard (AES), is applied. We show results of our methodology by developing a deciphering hardware accelerator that enables the LTE protocol stack to process data rates of 100 Mbit/s and beyond.

A new Q-enhancement architecture for SAW-less communication receiver in 65-nm CMOS

A 2.5V second order RF bandpass filter is presented. A new Q-enhancement structure stacked on a LNA is fabricated in a 65-nm CMOS process with a die area of 1.1 mm × 1.1 mm. The frequency range is adjustable in a 25% range from 1.7 GHz to 2.2 GHz while the Q is adjustable up to 50. Q and the center frequency are adjusted by binary weighted switchable capacitors. The filter draws 42 mA including the buffers from a 2.5 V supply and has an input referred out-of-band 1-dB compression point of 0 dBm. The measured in-band NF is between 5.4 and 6.2 dB.

Power analysis and optimization of the ZUC stream cipher for LTE-Advanced mobile terminals

In this paper we devise and compare several hardware implementations of the confidentiality algorithm that is based on the ZUC stream cipher. First we design and analyze a reference architecture, which reflects a basic implementation of the algorithm, with respect to power and area consumption in order to identify designs bottlenecks. Then different architectures for the most power demanding operations are explored to reduce the power consumption at the register transfer level. These architectures are evaluated at various timing constraints to account for data rates from LTE up to LTE-Advanced. The hardware analysis is done using Faradays 90 nm standard cell library. Our results show that 19% of power savings with 2% of area reduction can be achieved by using a cryptographic substitution box with one-hot encoding. When combining this with parallel LFSR architectures, power savings can be raised up to 37%, but with an area overhead of 10%.

Radar Distance Measurements in Over-sized Circular Waveguides

One of the main tasks of industrial radar systems is the determination of distances to a reflecting object. An important application is the measurement in metal tubes e.g. by means of the FMCW method. A comparison of measurements in metal tubes and in free-space shows that several problems arise due to the non-perfect coupling between the feeding antenna and the metal tube. This contribution describes the problems caused by dispersions and multi-mode propagations, and presents approaches for their solution

Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals

In this paper we investigate hardware implementations of ciphering algorithms, SNOW 3G and the Advanced Encryption Standard (AES), for the acceleration of the protocol stack layer 2 in the 3G Long Term Evolution (LTE). This analysis is based on timing requirements from execution time measurements in a simulated mobile phone platform, where we apply data rates of 100 Mbit/s and above (200 and 300 Mbit/s) to account for LTE and beyond LTE investigations. Different architectures for both algorithms are explored in order to meet the performance requirements, while keeping the power and area budget at a reasonable level. Therefore, a hardware analysis is done using a standard cell library of Faradays 90nm CMOS technology. Finally, the cryptographic substitution box with one-hot encoding emerges as the best solution for both ciphering schemes. Additionally, the 128-bit data path in the AES is identified as the most suitable architecture for LTE terminals, whereas a dual-AES approach turns out to be a candidate for data rates far beyond LTE (like LTE-Advanced).

Improved RF-performance of sub-micron CMOS transistors by asymmetrically fingered device layout

This paper presents novel MOS-transistor layouts for analog RF applications. Asymmetrical drain and source diffusion areas as well as their contacting metal stacks are adjusted to improve the transistor performance. These modifications allow for increased device currents and reduced parasitic wiring capacitances simultaneously. Ring oscillators with transistors of identical channel width and length fabricated in a 65 nm digital CMOS technology are used for verification. An increase of 14% in oscillation frequency compared to classical multi-finger layouts corroborates the improvement by these modifications.