Sebastian Hessel

Performance analysis of LTE protocol processing on an ARM based mobile platform

In this paper we present detailed profiling results and identify the time critical algorithms of the Long Term Evolution (LTE) layer 2 (L2) protocol processing on an ARM based mobile hardware platform. Furthermore, we investigate the applicability of a single ARM processor combined with a traditional hardware acceleration concept for the significantly increased computational demands in LTE and future mobile devices. A virtual prototyping approach is adopted in order to simulate a state-of-the-art mobile phone platform which is based on an ARM1176 core. Moreover a physical layer and base station emulator is implemented that allows for protocol investigations on transport block level at different transmission conditions. By simulating LTE data rates of 100 Mbit/s and beyond, we measure the execution times in a protocol stack model which is compliant to 3GPP Rel.8 specifications and comprises the most processing intensive downlink (DL) part of the LTE L2 data plane. We show that the computing power of a single embedded processor at reasonable clock frequencies is not enough to cope with the L2 requirements of next generation mobile devices. Thereby, Robust Header Compression (ROHC) processing is identified as the major time critical software algorithm, demanding half of the entire L2 DL execution time. Finally, we illustrate that a conventional hardware acceleration approach for the encryption algorithms fails to offer the performance required by LTE and future mobile phones.

Acceleration of the L4/Fiasco microkernel using scratchpad memory

In this paper we analyze the potential of using scratchpad memory in embedded devices to accelerate the operation of the L4/Fiasco microkernel affecting basically all applications on top of the kernel including virtualization software. We examine several low-level L4 system calls using a virtual prototype of Infineons S-GOLD® platform for mobile phones based on an ARM11 processor. We present a profiling strategy identifying critical parts of the microkernel to be placed on the scratchpad memory. Applying this approach we achieve a worstcase speedup of up to 29% with one page of scratchpad memory (4 kB) and up to 63% with two pages. With regard to the real-time capability of Fiasco, worst-case interrupt latency can be improved by almost 45% with only 4 kB of scratchpad memory.

On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals

In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data plane processing of the LTE protocol stack layer 2 (L2) in downlink direction. For this purpose, a hybrid design approach is adopted allowing first investigations of future mobile phone platforms on the system level (using virtual prototyping) combined with more accurate power-area explorations of hardware accelerators on the architectural level. Additionally, we show the employment of an LTE data generator peripheral, realizing L2 uplink processing and thus enabling platform analyses in a closed virtual environment. Furthermore, a modeling technique for a fast and efficient design of virtual hardware accelerator peripherals is demonstrated. A reasonable hardware/software partitioning can thereby be achieved early in the design phase. Once the system architecture is settled and thus the solution space is reduced, VHDL models of the accelerators are developed in order to find a suitable hardware implementation for LTE terminals based on timing constraints by system level simulations. As a case study, the LTE ciphering scheme, including the Advanced Encryption Standard (AES), is applied. We show results of our methodology by developing a deciphering hardware accelerator that enables the LTE protocol stack to process data rates of 100 Mbit/s and beyond.

On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices

In this paper we present a new on-the-fly hardware acceleration approach, based on a smart Direct Memory Access (sDMA) controller, for the layer 2 (L2) downlink protocol stack processing in Long Term Evolution (LTE) and beyond mobile devices. We use virtual prototyping in order to simulate an ARM1176 processor based hardware platform together with the executed software comprising an LTE protocol stack model. The sDMA controller with diff erent hardware accelerator units for the time critical algorithms in the protocol stack is implemented and integrated in the hardware platform. We prove our new hardware/software partitioning concept for the LTE L2 by measuring the average execution time per transport block in the protocol stack at di fferent activated on-the-fly hardware acceleration stages in the sDMA controller. At LTE data rates of 100 Mbit/s, we achieve a speedup of 24% compared to a pure software implementation by enabling the sDMA hardware support for header processing in the protocol stack. Furthermore, an activation of the complete on-the-fly hardware acceleration in the sDMA controller, including on-the-fly deciphering, leads to a speedup of more than 50 %. Finally, at transmission conditions with more computational demands and data rates up to 320 Mbit/s, we obtain acceleration ratios of almost 80 %. Investigations show that our new sDMA on-the-fly hardware acceleration approach in combination with a single-core processor off ers the required computational power for next generation mobile devices.

Joint Uplink and Downlink Performance Profiling of LTE Protocol Processing on a Mobile Platform

This article provides a detailed profiling of the layer 2 L2 protocol processing for 3G successor Long Term Evolution LTE. For this purpose, the most processing intensive part of the LTE L2 data plane is executed on top of a virtual ARM based mobile phone platform. The authors measure the execution times as well as the maximum data rates at different system setups. The profiling is done for uplink UL and downlink DL directions separately as well as in a joint UL and DL scenario. As a result, the authors identify time critical algorithms in the protocol stack and check to what extent state-of-the-art hardware platforms with a single-core processor and traditional hardware acceleration concepts are still applicable for protocol processing in LTE and beyond LTE mobile devices.

An optimized parallel and energy-efficient implementation of SNOW 3G for LTE mobile devices

Multi-core processors are becoming attractive for mobile devices because of the performance speedups and power savings they might attain. In this paper we employ such processors to investigate the SNOW 3G ciphering algorithm in the Long Term Evolution (LTE) protocol stack. In particular, we introduce several software optimizations, and present a novel parallel implementation of the algorithm. The proposed parallel design and its serial counterparts are then benchmarked using a simulated mobile phone platform. Evaluation results show that optimizations applied to the serial implementation saves 57% of energy consumption and shortens the execution time to the half. Moreover, the proposed parallel implementation meets the LTE speed, while reducing the energy consumption by 70%, and improving the energy efficiency by a factor of eight.

Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals

In this paper we investigate hardware implementations of ciphering algorithms, SNOW 3G and the Advanced Encryption Standard (AES), for the acceleration of the protocol stack layer 2 in the 3G Long Term Evolution (LTE). This analysis is based on timing requirements from execution time measurements in a simulated mobile phone platform, where we apply data rates of 100 Mbit/s and above (200 and 300 Mbit/s) to account for LTE and beyond LTE investigations. Different architectures for both algorithms are explored in order to meet the performance requirements, while keeping the power and area budget at a reasonable level. Therefore, a hardware analysis is done using a standard cell library of Faradays 90nm CMOS technology. Finally, the cryptographic substitution box with one-hot encoding emerges as the best solution for both ciphering schemes. Additionally, the 128-bit data path in the AES is identified as the most suitable architecture for LTE terminals, whereas a dual-AES approach turns out to be a candidate for data rates far beyond LTE (like LTE-Advanced).

Optimal resource management for a model driven LTE protocol stack on a multicore platform

The Long Term Evolution (LTE) is the successor technology of the 3G wireless system. The high data rates enabled by LTE can benefit from a strong computational power provided by todays high-performance embedded processors. In this work we therefore utilize a multicore processor to increase the LTE system throughput in the mobile terminal. We investigate the dynamic memory allocation scheme for the LTE protocol stack, modeled using Specification and Description Language (SDL), as the underlying issue with migrating from single to multiple cores. We discover that, under some schemes, multicore performance becomes inferior to a single-core, especially in case of intensive dynamic memory allocation and deallocation. By modifying the SDL systems run time kernel we implement a static memory management scheme. This is supplemented by a selective usage of resource protection in single- and dual-core situations. As a result, an increase of the system throughput by about 75% can be observed when migrating from one core to two cores.

Channel Equalization in HSDPA Receivers: Trade-Off between Performance and Complexity with a Variable Oversampling

In this paper algorithms for HSDPA receivers are investigated and optimized to achieve the specified performance while obtaining a low energy consumption. Different approaches including standard Rake combiner, MMSE and prefilter-Rake equalizers in combination with a variable oversampling ratio are discussed. The bit error rate (BER) is simulated within a complete fixed point physical layer model and the complexity of the different algorithms is compared. All equalizers fulfil the requirements of the specifications even for a vehicular propagation channel with a receiver velocity of 30 km/h. The prefilter-Rake equalizer using the Levinson algorithm reaches a throughput of 1.5 Mbit/s for SNR values greater than 6.1 dB. The comparison of performance and complexity demonstrates that the oversampling ratio can be tuned down to 2 samples per chip depending on the environment to reduce the complexity and energy consumption while maintaining the demanded performance

Exploration of energy efficient acceleration concepts for the ROHCv2 in LTE handsets

In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed and energy efficiency on system level. By applying a virtual prototyping methodology with a proprietary filter module, we are able to investigate these two approaches within a state-of-the-art ARM based mobile phone platform at real software loads. Additionally, combined measurements of the execution time together with an estimation of the energy, that is consumed in the memory and the bus architecture, are performed. With reasonably dimensioned scratchpad memories (16 kB for instructions and data respectively), maximum speedups and energy savings both of approximately 60 % are achieved depending on the cache sizes in the embedded processor. Even better performance, especially in combination with big caches, is reached with a dedicated ROHCv2 hardware accelerator supporting the processing of several packets at once in a so called list mode. Compared to the pure software case, the execution time and the energy consumption are both improved by up to 80 % at small caches and still amount to more than 40 % and almost 30 % at big caches, respectively.