Shadi Traboulsi

An Evaluation of Microkernel-Based Virtualization for Embedded Real-Time Systems

Devices for the mobile market have to satisfy a set of challenging constraints. In addition to the classical power, reliability and cost constraints, modern devices often have to be open to third party applications and at the same time provide a closed and secure environment for system functionality. In current systems, this antagonism is solved by maintaining a physical separation of subsystems with contrary constraints. Virtualization technology is a promising solution to safely merge conflicting subsystems on a single processor which leads to huge cost benefits and higher flexibility. Microkernel based hyper visors are an attractive choice for virtualization, due to their reliability and robustness. However, the involvement of real-time constraints remains a challenging factor. In this paper, we investigate how the security and isolation features of the L4/Fiasco microkernel impact real-time applications by comparing thread switching times and interrupt latencies to those of a conventional Real-time Operating System (RTOS). In addition, we demonstrate that microkernel based systems require significantly more cache resources than traditional systems. Finally, we investigate the performance loss caused by cache and TLB interference imposed by an application subsystem which runs in parallel to the real-time subsystem.

On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals

In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data plane processing of the LTE protocol stack layer 2 (L2) in downlink direction. For this purpose, a hybrid design approach is adopted allowing first investigations of future mobile phone platforms on the system level (using virtual prototyping) combined with more accurate power-area explorations of hardware accelerators on the architectural level. Additionally, we show the employment of an LTE data generator peripheral, realizing L2 uplink processing and thus enabling platform analyses in a closed virtual environment. Furthermore, a modeling technique for a fast and efficient design of virtual hardware accelerator peripherals is demonstrated. A reasonable hardware/software partitioning can thereby be achieved early in the design phase. Once the system architecture is settled and thus the solution space is reduced, VHDL models of the accelerators are developed in order to find a suitable hardware implementation for LTE terminals based on timing constraints by system level simulations. As a case study, the LTE ciphering scheme, including the Advanced Encryption Standard (AES), is applied. We show results of our methodology by developing a deciphering hardware accelerator that enables the LTE protocol stack to process data rates of 100 Mbit/s and beyond.

Modeling LTE protocol for mobile terminals using a formal description technique

The Long Term Evolution (LTE) radio communication is the upgrade of the current 3G mobile technology with a more complex protocol in order to enable very high data rates. The usage of Model Driven Development (MDD) has arisen as a promising way of dealing with the increasing complexity of next generation mobile protocols. In this paper, a light version of the LTE protocol for the access stratum user plane is modeled using the SDL Suite™ tool. The tool shows easy understanding of the model as well as easy testing of its functionality using simulation in cooperation with Message Sequence Chart (MSC). The simulation result shows that the implemented Specification and Description Language (SDL) guarantees a good consistency with the target scenarios. The system implementation is mapped to multiple threads and integrated with an operating system to enable execution in multi core hardware platforms.

Power analysis and optimization of the ZUC stream cipher for LTE-Advanced mobile terminals

In this paper we devise and compare several hardware implementations of the confidentiality algorithm that is based on the ZUC stream cipher. First we design and analyze a reference architecture, which reflects a basic implementation of the algorithm, with respect to power and area consumption in order to identify designs bottlenecks. Then different architectures for the most power demanding operations are explored to reduce the power consumption at the register transfer level. These architectures are evaluated at various timing constraints to account for data rates from LTE up to LTE-Advanced. The hardware analysis is done using Faradays 90 nm standard cell library. Our results show that 19% of power savings with 2% of area reduction can be achieved by using a cryptographic substitution box with one-hot encoding. When combining this with parallel LFSR architectures, power savings can be raised up to 37%, but with an area overhead of 10%.

An optimized parallel and energy-efficient implementation of SNOW 3G for LTE mobile devices

Multi-core processors are becoming attractive for mobile devices because of the performance speedups and power savings they might attain. In this paper we employ such processors to investigate the SNOW 3G ciphering algorithm in the Long Term Evolution (LTE) protocol stack. In particular, we introduce several software optimizations, and present a novel parallel implementation of the algorithm. The proposed parallel design and its serial counterparts are then benchmarked using a simulated mobile phone platform. Evaluation results show that optimizations applied to the serial implementation saves 57% of energy consumption and shortens the execution time to the half. Moreover, the proposed parallel implementation meets the LTE speed, while reducing the energy consumption by 70%, and improving the energy efficiency by a factor of eight.

High-performance and energy-efficient sliced AES multi-block encryption for LTE mobile devices

In this paper we present an efficient software implementation of the Advanced Encryption Standard (AES) used in the confidentiality algorithm of the Long Term Evolution (LTE) protocol. Our implementation is based on slicing and merging the bytes of several data blocks to exploit processors architecture width for multi-block encryption. In addition, an appropriate lookup table and data organization in memory are applied, combined with media processing instructions in order to enhance the performance of AES in embedded environments. Other optimized software implementations from literature are also explored and evaluated in comparison to the proposed implementation with respect to processing throughput and energy consumption using a multi-core based mobile phone platform. Simulation results show that the proposed implementation is the fastest among other implementations and achieves improvements in performance up to 69% while providing 59% of energy savings. Moreover, the presented implementation is scalable for multi-core execution. When running on two cores, it fulfills the LTE data rate of 100 Mbit/s and extends energy savings to 68%, leading to a total of 13 times improvement in energy efficiency.

An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals

In this paper we present an efficient hardware architecture for accelerating the Robust Header Compression version 2 (ROHCv2) algorithm in Long Term Evolution (LTE) mobile devices. The proposed hardware accelerator and its software variant are evaluated on an FPGA-based SoC. Our results show that the advised hardware architecture provides processing speeds (2.9 Gbit/s) beyond LTE-Advanced. Moreover, it increases the compression speed by 14-fold and reduces power consumption by 37%, compared to the software solution. The hardware is further optimized to handle multiple packet flows by employing a shared context buffer, thereby lowering the energy consumption of the ROHC hardware by 21% and ceasing degradation in compression rate.

An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs

Due to the multi-processor nature of Network Processors (NP), data packets entering the system are processed in parallel and might be transmitted out-of-order at the output leading to a significant degradation in network performance. In this paper we propose a new well-structured, area-efficient, and high speed hardware architecture for packet re-sequencing. For this purpose, several buffering techniques were investigated and analyzed in terms of complexity and memory requirements, taking into consideration the networking application and the impact of the number of processing elements (PE) on packet reordering. The proposed architecture, based on the appropriate buffering mechanism, is then demonstrated and implemented on our FPGA-based prototyping platform. In contrast to other solutions, our results showed 80% more efficient resource utilization while being capable to achieve 10% higher data rate of 3.2 Gbit/s. Keywords-Network Processors, Packet Reordering, Hardware Architecture, Multi-Processor System-on-Chip.

An Energy Efficient Multi-Core Modem Architecture for LTE Mobile Terminals

Since data rate in wireless communication systems has exponentially increased during the last decade, serious efforts are considered to fulfill their target requirements. Therefore, providing a satisfactory hardware to support high data rates while minimizing power consumption is a key design challenge for Long Term Evolution (LTE) mobile terminals. In this paper we introduce an optimized parallel software architecture for LTE mobile terminals using an energy aware scheduling and load balancing. We show that the proposed software architecture on single, dual, triple and quad-core hardware platforms leads to up to 39% energy savings. In addition, different hardware design options are investigated in order to minimize the average power consumption. The homogeneous multi-core with four cores processing the optimized LTE software saves about one quarter of the energy compared to a single-core running at higher clock frequency achieving the same data rate. Considering statistics for the mobile user behavior, the homogeneous multi-core with four cores proves to provide the minimum average power consumption compared to the other hardware architectures considered in this work.

Exploration of energy efficient acceleration concepts for the ROHCv2 in LTE handsets

In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed and energy efficiency on system level. By applying a virtual prototyping methodology with a proprietary filter module, we are able to investigate these two approaches within a state-of-the-art ARM based mobile phone platform at real software loads. Additionally, combined measurements of the execution time together with an estimation of the energy, that is consumed in the memory and the bus architecture, are performed. With reasonably dimensioned scratchpad memories (16 kB for instructions and data respectively), maximum speedups and energy savings both of approximately 60 % are achieved depending on the cache sizes in the embedded processor. Even better performance, especially in combination with big caches, is reached with a dedicated ROHCv2 hardware accelerator supporting the processing of several packets at once in a so called list mode. Compared to the pure software case, the execution time and the energy consumption are both improved by up to 80 % at small caches and still amount to more than 40 % and almost 30 % at big caches, respectively.