Joseph Aziz

8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS

This paper details a duplex architecture coupled with a linear Class-AB push-pull output stage that maximizes the power efficiency of linear wideband drivers for high-speed transceivers. The duplex driver merges transmission, reception, and termination; eliminates hybrid and termination overhead; and enables adaptive echo cancellation and rail-to-rail full-duplex operation. Implemented in 28 nm CMOS, this GPHY driver passes the 1000BASE-T and 100BASE-TX compliance tests using a 2.5 V supply and meets the transmit specifications for the half-duplex 10BASE-T Ethernet using a 3.3 V supply.

A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications

A self-terminated line driver suitable for fast Ethernet operates in class AB mode and combines digital signal processing with low-power analog circuits. It dissipates 108mW, 48% less than an existing state-of-the-art design. It occupies 0.22mm2 in a 65nm standard CMOS technology and operates from a 2.5V supply.