Joseph C. Ross

Electrochemical reactions in solder mask of flip chip-plastic ball grid array package

A typical flip chip plastic ball grid array (FC-PBGA) module utilizes a laminate substrate, which has a solder mask layer at the surface and a number of build-up layers. During reliability testing of the assembled chip-laminate modules under elevated temperature, humidity and voltage bias conditions, electrochemical reactions can proceed in the solder mask layer producing various oxidized copper (Cu) compounds and metallic Cu. If metallic Cu dendrites grow from one electrode toward its adjacent electrode, such dendrites can cause electrical leakage. The electrochemical reactions summarized in this paper involve ionic current flow between flip chip attach copper pads, impurity Cl- ions catalyzing Cu corrosion, the state of the solder mask and/or an absence of oxygen. Under the condition of 130°C, 85% relative humidity and 3.7V bias, Cu2+ ions move from an anode (power) or its vicinity toward a cathode (ground). Cu2+ ions are then reduced at the cathode to yield metallic Cu. If the reduced Cu forms a dendrite pointing toward the neighboring anode, the electric field will focus at the tip of the dendrite. Subsequently more Cu2+ ions will move toward the tip of the dendrite so that the dendrite keeps growing toward the anode. Lack of O2 under the highly accelerated stress conditions can also promote such dendrite growth since O2, if present, can be reduced at the cathode where the reduction of Cu2+ ions will decrease accordingly as a total number of electrons consumed for all reduction reactions remain constant. Cu dendrites can also grow from unbiased Cu electrodes due to the combined effect of galvanic cells and bipolar circuits.

Challenges of chip-to-package interaction for 22nm technology with ultra low k and Pb-free interconnects

A review of the chip-to-package interaction (CPI) results during the development and qualification of IBMs 22SOI high performance technology will be presented. Initial results and failure modes using ultra low-k (ULK) dielectric BEOL during the early development phase are shown. The fail modes include BEOL cracking under solder pads due to ULK formulations, from both planned material formulations and material properties related to tool excursion events, and leakage failures under high temperature, bias, and moisture attributed to incomplete formation of die edge seal. Full qualification data on a final robust process showing excellent CPI performance for this technology node are presented.

Capacitors on organic modules: a new THB failure mode and method of detection

Multi-terminal low inductance capacitors (MTLICs) are used widely throughout the electronics industry to aid with voltage noise suppression and to manage high speed switching currents. They are implemented on system level cards as well as microprocessors and ASICs. MTLIC component dimensions are getting smaller with increased requirements on capacitance/inductance, driving more Ni plates (up to ∼160), thinner dielectrics and therefore resulting in an increased risk for failure in temperature, humidity and bias stressing. Traditionally, MTLICs have been more robust than the modules they are used on - but this may be changing.

Multi-terminal low inductance capacitor delamination failure

The following details a new test methodology offered as a cost effective alternative to module form-factor testing for detecting the delamination fail mode observed in Multiterminal low inductance capacitors (MTLICs) under temperature humidity bias (THB) reliability stress testing. This MTLIC test methodology yields the same delamination reliability failure-mode as observed in the module form-factor. We draw on this new testing methodology to highlight the influence of packaging materials, module form factor and component supplier on THB reliability performance of MTLIC components.