Charles L. Arvin

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.

Effect of Ag and Cu content in Sn based Pb-free solder on electromigration

The effect of Ag and Cu concentrations on the electromigration of Pb-free solder was investigated. A nine cell experiment with Ag concentrations ranging from 1.2% to 2.2% and Cu concentrations ranging from 0.2 to 2.7% was conducted. Although the EM performance was found to be insensitive to the Ag and Cu concentrations in the range of the study, solder with 1.7% Cu showed the least Ag content dependence. EM failures occurred primarily on the substrate side. An effect of Sn grain texture with Ag and Cu concentrations was also observed.

Electrochemical reactions in solder mask of flip chip-plastic ball grid array package

A typical flip chip plastic ball grid array (FC-PBGA) module utilizes a laminate substrate, which has a solder mask layer at the surface and a number of build-up layers. During reliability testing of the assembled chip-laminate modules under elevated temperature, humidity and voltage bias conditions, electrochemical reactions can proceed in the solder mask layer producing various oxidized copper (Cu) compounds and metallic Cu. If metallic Cu dendrites grow from one electrode toward its adjacent electrode, such dendrites can cause electrical leakage. The electrochemical reactions summarized in this paper involve ionic current flow between flip chip attach copper pads, impurity Cl- ions catalyzing Cu corrosion, the state of the solder mask and/or an absence of oxygen. Under the condition of 130°C, 85% relative humidity and 3.7V bias, Cu2+ ions move from an anode (power) or its vicinity toward a cathode (ground). Cu2+ ions are then reduced at the cathode to yield metallic Cu. If the reduced Cu forms a dendrite pointing toward the neighboring anode, the electric field will focus at the tip of the dendrite. Subsequently more Cu2+ ions will move toward the tip of the dendrite so that the dendrite keeps growing toward the anode. Lack of O2 under the highly accelerated stress conditions can also promote such dendrite growth since O2, if present, can be reduced at the cathode where the reduction of Cu2+ ions will decrease accordingly as a total number of electrons consumed for all reduction reactions remain constant. Cu dendrites can also grow from unbiased Cu electrodes due to the combined effect of galvanic cells and bipolar circuits.

Capacitors on organic modules: a new THB failure mode and method of detection

Multi-terminal low inductance capacitors (MTLICs) are used widely throughout the electronics industry to aid with voltage noise suppression and to manage high speed switching currents. They are implemented on system level cards as well as microprocessors and ASICs. MTLIC component dimensions are getting smaller with increased requirements on capacitance/inductance, driving more Ni plates (up to ∼160), thinner dielectrics and therefore resulting in an increased risk for failure in temperature, humidity and bias stressing. Traditionally, MTLICs have been more robust than the modules they are used on - but this may be changing.