Sylvain Ouimet

From Leaded to Lead Free Assembly and New Packaging Technology Challenges

The migration to lead free connections in the microelectronic industry has brought forth many technical challenges, especially in the packaging technology area with respect to materials and processes. The two major drivers to these challenges are the higher melting point and the thermo-mechanical behaviour (less creep than SnPb alloy) of the replacement alloy. The higher melting point drives higher reflow temperatures during the packaging assembly as well as the card assembly and this requires the use of new materials. Higher stresses in the package can result in a reliability impact for the product. The challenge of these lead free related changes is exacerbated by other trends in leading edge organic packaging such as chip low K dielectric materials, larger package and larger chip dimensions and, reduced chip bump pitch. This paper provides the reliability results obtained through various lead free organic package test matrices and qualifications. The principal failure mechanisms are presented and are explained through material properties and finite element modeling studies. Details of the package technology qualification process and results are presented.

Router flip chip packaging solution and reliability

In January 2000, the requirements and functional specifications for a family of high availability core routers were defined and drove the development of six custom VLSI devices using large FCCGA (flip chip column grid array) packages with large devices. Such combinations have always been a challenge for first level packaging as well as second level reliability. For this specific application, a 58 mm ceramic carrier with device sizes up to 21 mm required qualification and to be brought into production with high reliability performance. This paper describes the qualification strategy and structure used by the IBM flip chip assembly site located in Bromont (Quebec, Canada) as well as the test vehicle used to support end product reliability requirements. In addition, stress testing results are discussed, covering 1/sup st/ and 2/sup nd/ level packaging.

Packaging aspects of the Jitney parallel optical interconnect

The Jitney parallel optical interconnect is a prototype 20-channel wide, low cost data link, designed for operation at speeds up to one Gbyte/s over distances approaching 100 meters. The package is based on (1) an inexpensive overmolded leadframe, (2) passive optical alignment, and (3) plastic molded parts. The packaging challenges in the fabrication of the components, their assembly, and in the achievement of the performance goals are described.

Development of a 50mm dual Flip Chip Plastic Land Grid Array package for server applications

For many years, the Flip Chip Plastic Ball Grid Array (FC-PBGA) has been the preferred packaging solution for microprocessors and high performance ASICs. IBM has developed a dual chip Flip Chip Plastic Land Grid Array (FC- PLGA) package to support low and mid range server solutions. This organic 50 mm times 50 mm lead reduced package solution uses a 6-4-6 build-up laminate with two large chips consisting of a processor (22 times 16 mm) and a memory cache (15 times 13 mm) in a single piece lid capping solution. In this paper, we will summarize development activities performed in order to achieve a reliable product while dissipating up to 200 Watts mostly from the microprocessor chip. One of the many key issues to overcome was the assurance of good package thermal stability with such large silicon area coverage over the flexible organic chip carrier. Special chip and module test vehicles were designed and fabricated in order to evaluate the mechanical, electrical, and thermal behaviour of the package post assembly and throughout stress testing. The assembly process development activities performed to support the desired application will be discussed in conjunction with mechanical modeling results. In addition, thermal data will be presented showing the positive results obtained as well as good correlation to the thermal and mechanical models.

Hybrid assembly technology for flip-chip-on-chip (FCOC) using PBGA laminate assembly

Component integration is becoming more and more popular to achieve reduction of space with increasing performance of electronic packages. Dual-Chip-Stack (DCS) is the direct, face to face joining of two (or more) semiconductor devices. It improves significantly component integration by leveraging flip-chip technology processing, standard wirebond packaging and plastic ball grid array (PBGA) processes. High bandwidth interconnections between devices of various process technologies allow the construction of unique, high margin component assemblies. In this paper, the authors describe the assembly development work of a DCS package using a logic device attached to a DRAM device over a PBGA chip-up type carrier. Proposed packaging flow is discussed with process modifications to obtain a robust product. The processes discussed are: flip-chip dicing, device to device joining, wirebond to laminate carrier, and encapsulation (Underfill and Globtop). Some reliability results will also be shown and discussed.

Overmold technology applied to cavity down ultrafine pitch PBGA package

The transfer molding technology is normally used for leadframe type packages and chip-up PBGA (Plastic Ball Grid Array) packages. This technology has been applied to cavity down PBGA packages where, normally, a liquid epoxy is dispensed by a needle in the cavity in order to cover the device and gold wires without exceeding the solder ball height plane. The new encapsulation approach using transfer molding process as well as the debug/qualification method and results using an ultrafine pitch wirebond PBGA process are described.

Module camber effect on card assembly and reliability for large flip chip BGA organic packages

Component manufacturers and card assemblers are regularly confronted by the specification limits for the coplanarity of electronic components, and the effects of component warp age over the temperature range encountered during reflow processes used during card assembly. Card level assembly defects are often imputable to incompatible planarity levels of raw cards and their associated components, but the resultant impact of coplanarity mismatch is not well understood from the perspective of primary assembly yields at card joining and reliability. The present work studies the effect of module level camber on assembly yields and the reliability of a 55 mm x 55 mm, 2809 I/O FCPBGA component with lead free second level solder joints. The coplanarity of the components was modulated by applying different capping strategies, such as variation in heat spreader thickness, design, and attach process to achieve a range of coplanarties, including some well above current specifications, as measured at room temperature. Component coplanarity was measured for each component, and the warpage behaviour of each component variation throughout a reflow profile with a peak temperature of 240degC was also characterized. Module and card assembly limitations and the resultant solder joint geometries are further detailed in this work. Following assembly, the test vehicles were subjected to accelerated thermal cycling. The failures observed in the assemblies as a result of thermal cycling occurred in the second level ball grid array joints, located mostly in the center area of the package around the die shadow. The current study enabled the identification of the principal factors affecting the failure rates of the solder ball grid array, which include the board thickness, component design parameters such as heat spreader configuration and die size, and the shape of the solder balls, which is a function of the difference in height resulting from PCB and module warpage at the solidification temperature. Interestingly, room temperature coplanarity was not a strong indicator of reliability in this study. The work emphasizes the importance of achieving module to card coplanarity near solder reflow temperatures.

Challenges of chip-to-package interaction for 22nm technology with ultra low k and Pb-free interconnects

A review of the chip-to-package interaction (CPI) results during the development and qualification of IBMs 22SOI high performance technology will be presented. Initial results and failure modes using ultra low-k (ULK) dielectric BEOL during the early development phase are shown. The fail modes include BEOL cracking under solder pads due to ULK formulations, from both planned material formulations and material properties related to tool excursion events, and leakage failures under high temperature, bias, and moisture attributed to incomplete formation of die edge seal. Full qualification data on a final robust process showing excellent CPI performance for this technology node are presented.

Capacitors on organic modules: a new THB failure mode and method of detection

Multi-terminal low inductance capacitors (MTLICs) are used widely throughout the electronics industry to aid with voltage noise suppression and to manage high speed switching currents. They are implemented on system level cards as well as microprocessors and ASICs. MTLIC component dimensions are getting smaller with increased requirements on capacitance/inductance, driving more Ni plates (up to ∼160), thinner dielectrics and therefore resulting in an increased risk for failure in temperature, humidity and bias stressing. Traditionally, MTLICs have been more robust than the modules they are used on - but this may be changing.

Multi-terminal low inductance capacitor delamination failure

The following details a new test methodology offered as a cost effective alternative to module form-factor testing for detecting the delamination fail mode observed in Multiterminal low inductance capacitors (MTLICs) under temperature humidity bias (THB) reliability stress testing. This MTLIC test methodology yields the same delamination reliability failure-mode as observed in the module form-factor. We draw on this new testing methodology to highlight the influence of packaging materials, module form factor and component supplier on THB reliability performance of MTLIC components.