Joseph J. Nahas

A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers

A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional programming currents controlled by locally mirrored write drivers to apply a robust toggle write sequence. An isolated read architecture driven by a balanced three input current mirror sense amplifier supports 25-ns cycle time asynchronous operation.

Two-Dimensional Heterojunction Interlayer Tunneling Field Effect Transistors (Thin-TFETs)

Layered 2-D crystals embrace unique features of atomically thin bodies, dangling bond free interfaces, and step-like 2-D density of states. To exploit these features for the design of a steep slope transistor, we propose a Two-dimensional heterojunction interlayer tunneling field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) of ~14 mV/dec and a high on-current of ~300 μm are estimated theoretically. The SS is ultimately limited by the density of states broadening at the band edges and the on-current density is estimated based on the interlayer charge transfer time measured in recent experimental studies. To minimize supply voltage VDD while simultaneously maximizing on currents, Thin-TFETs are best realized in heterostructures with near broken gap energy band alignment. Using the WSe2/SnSe2 stacked-monolayer heterostructure, a model material system with desired properties for Thin-TFETs, the performance of both n-type and p-type Thin-TFETs is theoretically evaluated. Nonideal effects such as a nonuniform van der Waals gap thickness between the two 2-D semiconductors and finite total access resistance are also studied. Finally, we present a benchmark study for digital applications, showing the Thin-TFETs may outperform CMOS and III-V TFETs in term of both switching speed and energy consumption at low-supply voltages.

Demonstrated reliability of 4-mb MRAM

The successful commercialization of MRAM will rely on providing customers with a robust and reliable memory product. The intrinsic reliability of magnetoresistive tunnel junction (MTJ) memory bits and the metal interconnect system of MRAM are two areas of great interest due to the new materials involved in this emerging technology. Time dependent dielectric breakdown (TDDB) and resistance drift were the two main failure mechanisms identified for intrinsic memory bit reliability. Results indicated that a lifetime over 10 years is achievable under the operating condition. For metal interconnect system, the initial results of Cu with magnetic cladding have met the reliability performance of typical nonclad Cu backend process in electromigration (EM) and iso-thermal annealing (ITA). Finally data retention is demonstrated over times orders of magnitude longer than 10 years.

Analog Circuit Design Using Tunnel-FETs

Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities. Comparing 14-nm III-V TFET-based OTAs with Si-MOSFET-based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail.

Magnetic–Electrical Interface for Nanomagnet Logic

We present simulations of, and design alternatives for, an interface between nanomagnet logic (NML) and electrical circuitry. We propose using the fringing fields from a nanomagnet to help set the state of the free layer of a magnetic tunnel junction (MTJ). Our first magnetic-electrical interface design (MEI-1) assumes an MTJ stack layout, commonly seen in commercial magnetoresistive random access memory (MRAM). Our second design (MEI-2) is also based on a traditional MRAM process flow, but layers of the MTJ are deposited in reverse order. In MEI-2, the NML devices have the same thickness as the MTJ free layer. Simulations for MEI-2 suggest that the layer thickness and size are important design parameters, when considering realistic implementations of this MEI. By comparison, MEI-2 is applicable for the present process technology, while MEI-1 would be more easily fabricated with further technology development.

TFET-based cellular neural network architectures

It is well known that CMOS scaling trends are now accompanied by less desirable byproducts such as increased energy dissipation. To combat the aforementioned challenges, solutions are sought at both the device and architectural levels. With this context, this work focuses on embedding a low voltage device, a Tunneling Field Effect Transistor (TFET) within a Cellular Neural Network (CNN) - a low power analog computing architecture. Our study shows that TFET-based CNN systems, aside from being fully functional, also provide significant power savings when compared to the conventional resistor-based CNN. Our initial studies suggest that power savings are possible by carefully engineering lower voltage, lower current TFET devices without sacrificing performance. Moreover, TFET-based CNN reduces implementation footprints by eliminating the hardware required to realize output transfer functions. Application dynamics are verified through simulations. We conclude the paper with a discussion of desired device characteristics for CNN architectures with enhanced functionality.

Nontraditional Computation Using Beyond-CMOS Tunneling Devices

Amongst potential post-CMOS technologies, tunnel field-effect transistors (TFETs) are attractive for low-power systems. While TFETs are functionally somewhat similar to MOSFETs, the newly proposed tunneling transistors such as SymFETs and BiSFETs demonstrate more “exotic” characteristics that are significantly different from MOSFETs. We look at the possible applications of TFETs and SymFETs for unconventional signal processing by employing their signature behaviors. We focus on networks of interconnected nonlinear elements which can process data coming from a large number of inputs (e.g., sensors) in an analog fashion. Specifically, we investigate several applications of TFET and SymFET in directional and anisotropic diffusion, estimating Gaussian distance of different patterns in analog associative memories, and estimating minimum/maximum or variance of analog data. We show that such circuits have reduced complexity and/or enhanced power efficiency.

Reliability of 4 Mbit MRAM

Prior to our recent publication (J. Akerman et al, IEEE Trans. Dev. Mat. Rel. 4, p.428-435, 2004), little data on magnetoresistive random access memory (MRAM) reliability were available in the literature. In this paper, we present additional reliability data taken in full 4 Mb MRAM arrays, significantly extending the scope of our original study. In particular, we present good reliability over 10 years against dielectric breakdown, resistance drift, drift of programming currents, electromigration, and also demonstrate solid data retention. This study further solidifies our expectations of MRAM becoming the memory technology of choice for high-performance non-volatile memory applications where endurance and reliability are crucial requirements.

Exploring the Design of the Magnetic–Electrical Interface for Nanomagnet Logic

Nanomagnet logic (NML) has received increasing attention as an alternative information processing technology given the potential for low energy dissipation, a relatively advanced experimental state of the art, and intangibles such as inherent radiation hardness and nonvolatility. In order to facilitate the integration of NML-based circuits with transistor-based circuits, a magnetic-electrical interface (MEI) is needed. This paper focuses on the output portion of MEI design, i.e., converting signals from the magnetic domain to the electrical domain. The basic idea of an MEI output is to employ fringing fields from an NML device to set the magnetization state of the free layer of a magnetic tunnel junction. A detailed study of four different MEI output designs is presented which considers metrics such as the clock energy required to set the output state, the magnetoresistance ratio, etc. Simulation-based analysis reveals the pros and cons of each design. A design where multiple NML devices (i.e., free layers) share a large synthetic antiferromagnet is most promising based on our simulation-based, quantitative analysis.

Boolean circuit design using emerging tunneling devices

Novel device technologies are exceedingly under investigation for the sub-10-nm era. Some tunneling devices employing 2-D materials have shown the potential for low-voltage operation, promising energy efficient digital circuits and systems. Interestingly, certain emerging tunneling devices such as SymFETs and BiSFETs exhibit an I-V characteristic different from that of MOSFETs. In this paper, the design of Boolean gates with SymFETs is studied. We show that the negative differential resistance (NDR) behavior of the transistors leads to hysteresis in inverters and buffers, and can be used to build simple Schmitttriggers. It can also by used in designing new pseudo-SymFET loads for circuits similar to all-n-type or dynamic logic. We demonstrate the feasibility of building NAND, NOR, IMPLY, and MAJORITY gates with fewer transistors when compared with static CMOS designs. Benchmarking efforts show that SymFETs are an attractive choice for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits; but one challenge for SymFET circuits is relatively larger leakage currents.