Behnam Sedighi

Analog Circuit Design Using Tunnel-FETs

Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors, and track-and-hold circuits are examined. It is shown that TFETs are promising for low-power and low-voltage designs, wherein transistors are biased at low-to-moderate current densities. Comparing 14-nm III-V TFET-based OTAs with Si-MOSFET-based designs demonstrates up to 5 times reduction in the power dissipation of the amplifiers and more than an order of magnitude increase in their DC voltage gain. The challenges and opportunities that come with the special characteristics of TFETs, namely asymmetry, ambipolar behavior, negative differential resistance, and superlinear operation are discussed in detail.

Nontraditional Computation Using Beyond-CMOS Tunneling Devices

Amongst potential post-CMOS technologies, tunnel field-effect transistors (TFETs) are attractive for low-power systems. While TFETs are functionally somewhat similar to MOSFETs, the newly proposed tunneling transistors such as SymFETs and BiSFETs demonstrate more “exotic” characteristics that are significantly different from MOSFETs. We look at the possible applications of TFETs and SymFETs for unconventional signal processing by employing their signature behaviors. We focus on networks of interconnected nonlinear elements which can process data coming from a large number of inputs (e.g., sensors) in an analog fashion. Specifically, we investigate several applications of TFET and SymFET in directional and anisotropic diffusion, estimating Gaussian distance of different patterns in analog associative memories, and estimating minimum/maximum or variance of analog data. We show that such circuits have reduced complexity and/or enhanced power efficiency.

Boolean circuit design using emerging tunneling devices

Novel device technologies are exceedingly under investigation for the sub-10-nm era. Some tunneling devices employing 2-D materials have shown the potential for low-voltage operation, promising energy efficient digital circuits and systems. Interestingly, certain emerging tunneling devices such as SymFETs and BiSFETs exhibit an I-V characteristic different from that of MOSFETs. In this paper, the design of Boolean gates with SymFETs is studied. We show that the negative differential resistance (NDR) behavior of the transistors leads to hysteresis in inverters and buffers, and can be used to build simple Schmitttriggers. It can also by used in designing new pseudo-SymFET loads for circuits similar to all-n-type or dynamic logic. We demonstrate the feasibility of building NAND, NOR, IMPLY, and MAJORITY gates with fewer transistors when compared with static CMOS designs. Benchmarking efforts show that SymFETs are an attractive choice for applications that demand low power and have moderate speed requirements, and demonstrate better dynamic energy efficiency than CMOS circuits; but one challenge for SymFET circuits is relatively larger leakage currents.

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study

A Cellular Neural Network (CNN) is a highly-parallel, analog processor that can significantly outperform von Neumann architectures for certain classes of problems. Here, we show how emerging, beyond-CMOS devices could help to further enhance the capabilities of CNNs, particularly for solving problems with non-binary outputs. We show how CNNs based on devices such as graphene transistors - with multiple steep current growth regions separated by negative differential resistance (NDR) in their I-V characteristics - could be used to recognize multiple patterns simultaneously. (This would require multiple steps given a conventional, binary CNN.) Also, we demonstrate how tunneling field effect transistors (TFETs) can be used to form circuits capable of performing similar tasks. With this approach, more “exotic” device I-V characteristics are not required - which should be an asset when considering issues such as cell-to-cell mismatch, etc. As a case study, we present a CNN-cell design that employs TFET-based circuitry to realize ternary outputs. We then illustrate how this hardware could be employed to efficiently solve a tactile sensing problem. The total number of computation steps as well as the required hardware could be reduced significantly when compared to an approach based on a conventional CNN.

Architectural impacts of emerging transistors

At present there is much effort to determine if emerging information processing devices could have a positive impact on the performance of non-Boolean/non-von Neumann computer architectures. We explore this topic here by specifically considering how emerging transistor technologies might impact cellular neural networks (CNNs). For CNNs, prior work suggests that new transistor structures could be employed to better facilitate non-binary outputs - that in turn reduce the number of template/programming operations as well as the hardware paths needed to solve a given problem. Here, we present analysis that considers how the above approach could impact the performance/energy of the cells that comprise the CNN. We also consider how characteristics of other emerging transistor technologies could positively impact CNNs - particularly with respect to reduced program complexity.

Cellular neural networks for image analysis using steep slope devices

Traditional CMOS based von Neumann architectures face daunting challenges in performing complex computational tasks at high speed and with low power on spatio-temporal data, e.g., image processing, pattern recognition, etc. In this study, we discuss the utilities of various steep slope, beyond-CMOS emerging devices for image processing applications within the non-von Neumann computing paradigm of cellular neural networks (CNNs). In general, the steep subthreshold swing of the devices obviates the output transfer hardware used in a conventional CNN cell. For image processing with binary stable outputs, Tunnelling FETs (TFETs) can facilitate low power operation. For multi-valued problems, devices like graphene transistors, Symmetric tunnelling FETs (SymFETs) might be leveraged to solve a problem with fewer computational steps. The potential for additional hardware reduction when compared to functional equivalents via conventional CNNs is also possible. Emerging devices can also lead to lower power implementations of the voltage controlled current sources (VCCSs) that are an integral component of any CNN cell. Furthermore, non-linear implementations of the VCCSs via emerging devices could enable simpler computational paths for many image processing tasks.

Design of latches and flip-flops using emerging tunneling devices

Tunneling field-effect transistors (TFETs) stand out among novel device technologies for low-power circuits and systems. While some TFETs exhibits behavior similar to MOSFETs, a group of emerging tunneling devices including symmetric tunneling FETs (SymFETs) and interlayer tunnel FETs (IFETs) demonstrate a bell-shaped I-V characteristic dissimilar to that of MOSFETs. They have shown the potential for image processing and nontraditional computing in analog applications and the design of Boolean gates with SymFETs has also been explored. This paper uses a SymFET as a proxy to design sequential circuits comprised of devices with bell-shaped I-V characteristics. Said circuits are essential as practically any application requires the indefinite storage of data and control modules during computation. We show that the negative differential resistance (NDR) behavior of SymFET transistors can be employed to build compact and low power latches and flip-flops. The relationship of SymFET with another well-known tunneling device, namely resonant tunneling diode (RTD), is investigated. We illustrate how previous research on RTD-based circuits - such as monostable-bistable (MOBILE) self-latching circuits and highly compact MOBILE-based D flip-flop circuits - can be adopted to SymFETs. Our paper provides a novel path of circuit designs based on devices that have characteristics similar to SymFETs and shows that SymFETs are a promising option for image processing applications in terms of power and area.

Timing errors in LDPC decoding computations with overscaled supply voltage

Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling (VOS) in their implementation to save energy. In this paper, the impact of VOS on timing errors is characterized for a typical min-sum LDPC decoder architecture using circuit simulations. Failure modes are analyzed for arithmetic circuits performing variable and check node computations. It is shown that a rather unconventional register placement in the variable node unit is beneficial for voltage scaling, and that the check node unit may be designed such that only the least significant bits are more likely to experience errors. Insights into timing error characteristics obtained through this analysis can be used to estimate the limits of voltage scaling and associated energy saving in practical LDPC decoder designs.

A CNN-inspired mixed signal processor based on tunnel transistors

Novel devices are under investigation to extend the performance scaling trends that have long been associated with Moores Law-based device scaling. Among the emerging devices being studied, tunnel FETs (or TFETs) are particularly attractive, especially when targeting low power systems. This paper studies the potential of analog/mixed-signal information processing using TFETs. The design of a highly-parallel processor - inspired by cellular neural networks - is presented. Signal processing is performed partially in the time-domain to better leverage the unique properties of TFETs, i.e., (i) steep slopes (high gm/IDS) in the subthreshold region, and (ii) high output resistance in the saturation region. Assuming an InAs TFET with feature sizes comparable to the 14 nm technology node, a power efficiency of 10,000 GOPS/W is projected. By comparison, state-of-the-art hardware assuming CMOS technology promises a power efficiency only close to 1,000 GOPS/W.