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Dive into the research topics where Joseph Jelemensky is active.

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Featured researches published by Joseph Jelemensky.


IEEE Journal of Solid-state Circuits | 1990

Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM

Clinton C. K. Kuo; Thomas R. Toms; B.T. Neel; Joseph Jelemensky; E.A. Carter; P. Smith

A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An extensive circuit analysis was made to establish the operation theory and special circuit design features required for SDD. Complete SDD circuits have been developed and implemented into a 16 K CMOS SRAM module for a 32-b microcontroller. Full operation and effectiveness of the SDD technique were verified from a special experimental 16 K CMOS RAM module with built-in defective cells. the SDD technique can accomplish not only the retention test at room temperature, but also the detection of other defects that were heretofore impractical to detect using the conventional retention test technique of high-temperature bakes and functional tests. >


IEEE Journal of Solid-state Circuits | 1992

A 512-kb flash EEPROM embedded in a 32-b microcontroller

Clinton C. K. Kuo; Mark S. Weidner; Thomas R. Toms; Henry Choe; K.-M. Chang; A. Harwood; Joseph Jelemensky; P. Smith

A 512-kb flash EEPROM developed for microcontroller applications is reported. Many process and performance constraints associated with the conventional flash EEPROM have been eliminated through the development of a new flash EEPROM cell and new circuit techniques. Design of the 512-kb flash EEPROM, which is programmable for different array sizes, has been evaluated from 256- and 384-kb arrays embedded in new 32-b microcontrollers. The 512-kb flash EEPROM has incorporated the newly developed source-coupled split-gate (SCSG) flash EEPROM cell, Zener-diode controlled programming voltages, internally generated erase voltage, and a new differential sense amplifier. It has eliminated overerase and program disturb problems without relying on tight process controls and on critical operational sequences and timings, such as intelligent erase, intelligent program, and preprogram before erase. A modular approach was used for chip design to minimize development time and for processing technology to achieve high manufacturability and flexibility. >


Archive | 1989

Queued serial peripheral interface for use in a data processing system

Susan C. Hill; Joseph Jelemensky; Mark R. Heene; Stanley E. Groves; Daniel N Debrito


Archive | 1993

Method and apparatus for performing multiplexed and non-multiplexed bus cycles in a data processing system

Oded Yishay; Joseph Jelemensky; Ann E. Harwood; Javier Saldana


Archive | 1991

Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal

Thomas R. Toms; Joseph Jelemensky; Hubert G. Carson; Mark R. Heene


Archive | 1994

Breakpoint detection circuit in a data processor and method therefor

Oded Yishay; Joseph Jelemensky


Archive | 1995

Reset configuration in a data processing system and method therefor

Oded Yishay; Joseph Jelemensky; Jeffrey D. Quinn; Daniel W. Pechonis


Archive | 1994

Integrated circuit data processor which provides external sensibility of internal signals during reset

Alexander L. Iles; Joseph Jelemensky; Oded Yishay


Archive | 1994

Data processor and method for providing show cycles on a fast multiplexed bus

Oded Yishay; Joseph Jelemensky; Alexander L. Iles


Archive | 1996

Flexible reset configuration of a data processing system and method therefor

Oded Yishay; Daniel W. Pechonis; Joseph Jelemensky

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