Clinton C. K. Kuo

Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM

A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An extensive circuit analysis was made to establish the operation theory and special circuit design features required for SDD. Complete SDD circuits have been developed and implemented into a 16 K CMOS SRAM module for a 32-b microcontroller. Full operation and effectiveness of the SDD technique were verified from a special experimental 16 K CMOS RAM module with built-in defective cells. the SDD technique can accomplish not only the retention test at room temperature, but also the detection of other defects that were heretofore impractical to detect using the conventional retention test technique of high-temperature bakes and functional tests. >

A 512-kb flash EEPROM embedded in a 32-b microcontroller

A 512-kb flash EEPROM developed for microcontroller applications is reported. Many process and performance constraints associated with the conventional flash EEPROM have been eliminated through the development of a new flash EEPROM cell and new circuit techniques. Design of the 512-kb flash EEPROM, which is programmable for different array sizes, has been evaluated from 256- and 384-kb arrays embedded in new 32-b microcontrollers. The 512-kb flash EEPROM has incorporated the newly developed source-coupled split-gate (SCSG) flash EEPROM cell, Zener-diode controlled programming voltages, internally generated erase voltage, and a new differential sense amplifier. It has eliminated overerase and program disturb problems without relying on tight process controls and on critical operational sequences and timings, such as intelligent erase, intelligent program, and preprogram before erase. A modular approach was used for chip design to minimize development time and for processing technology to achieve high manufacturability and flexibility. >

Low-defect-density and high-reliability FETMOS EEPROM's fabricated using furnace N/sub 2/O oxynitridation

The superior characteristics of floating-gate electron tunneling MOS (FETMOS) EEPROMs fabricated using a furnace N/sub 2/O oxynitridation process are described. These devices exhibited about eight times better endurance and good data retention characteristics while maintaining defect density comparable to that of the control thermal oxide devices. These devices also showed very good thickness uniformity across the wafer and wafer-to-wafer.<<ETX>>

A modular flash EEPROM technology for 0.8 mu m high speed logic circuits

A flash EEPROM technology has been integrated into a 0.8 mu m double-metal CMOS high-speed process for custom integrated circuit applications. The modular approach employed effectively decouples the double-poly, thick-oxide flash EEPROM process from the single-poly, thin-oxide host process. The flash EEPROM has a <100- mu s byte programming time and a nominal 1-s bulk erasure time. The low threshold voltage of the erased cell permits access without wait states at 3-V supply. This technology has been successfully demonstrated on a 32-b microcontroller with a 32-kbyte flash EEPROM module.<<ETX>>

A 32-bit RISC microcontroller with 448K bytes of embedded flash memory

This paper describes a sub-half micron embedded flash EEPROM developed for high speed microcontroller applications. A 32-bit RISC microcontroller with 448 kbytes (3.67 Mbits) of embedded flash EEPROM is presented. High density flash memory is achieved by utilizing a single transistor NOR type cell that employs Fowler-Nordheim electron tunneling for both program and erase. The high density flash EEPROM is integrated into a high performance logic process with dual gate oxides for high performance and high voltage transistors. The array program time is greatly reduced by employing a highly parallel program operation, and data throughput is greatly enhanced by a page mode operation. Operating at 40 MHz, the embedded flash memory has an on-chip off-page access time of under 38 ns and on-page access time of under 13 ns.

A new scalable floating-gate EEPROM cell

Abstract In a Floating-gate Thin Oxide (FLOTOX) MOS transistor, the dimension of the tunnel window and surrounding active area is a limiting factor in cell scaling. However, this limiting factor can be eliminated by opening a tunnel window which overlaps the field oxide. Experimental results show that the presence of the field oxide edges does not pose a reliability concern for the tunnel oxide quality in the new cell. Since the tunnel region is defined by the intersection of the tunnel window mask and the active area, the new cell eliminates the spacing between the tunnel window and the field oxide. Therefore, cell characteristics are insensitive to the tunnel window misalignment with respect to the field edges. Because the tunnel region area of the new cell is scalable, the floating gate transistor drain area and the overall cell size become scalable as the peripheral circuit device dimension is scaled down. Due to a smaller achievable drain area, the new cell shows a better programmability. For a target threshold voltage window, the required programming voltage as well as the isolation spacing between cells can be reduced. By controlling the doping profile around the tunnel region, a scalable EEPROM cell with reliability and uniformity comparable to the conventional FLOTOX cell has been achieved.

New submicron non-volatile memory modules for 16/32-bit devices

Development of new submicron non-volatile memory modules, including an EEPROM with unique programmable redundancy and a block erasable flash EEPROM, for 16-bit and 32-bit devices is reported. Optional process modules required for the non-volatile memories are developed for integration into the baseline logic process based on 0.65 mu double metal CMOS technology.<<ETX>>

A 32 bit microcontroller with an embedded flash EEPROM

The development of a versatile 32 bit microcontroller containing various peripheral functional modules including a 512 K bit flash EEPROM is described. A modular process approach was employed to integrate high voltage transistors and flash EEPROM cells into the baseline 08 mu m twin well double metal CMOS process. A modular circuit design approach was utilized to simplify chip design and to reduce development time.<<ETX>>