Paul A. LaBerge

Dynamic command and/or address mirroring system and method for memory modules

Latency reduction using negative clock edge and read flags

Method of peer-to-peer mastering over a computer bus

Device for blocking bus transactions during reset

Method and system for apportioning computer bus bandwidth

Memory devices with buffered command address bus

Memory system and method using stacked memory device dice, and system using the memory system

Delay line synchronizer apparatus and method

Programmable logic block in an integrated circuit

Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing