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Joseph Michael Fitzgerald

IBM

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Publication

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Archive | 1988

Macro structural arrangement and method for generating macros for vlsi semiconductor circuit devices

Anthony Gus Aipperspach; Douglas M. Dewanz; Joseph Michael Fitzgerald

Archive | 1998

Method and apparatus for estimating durations of activities in forming a current system, based on past durations of activities in forming past systems

Joseph Michael Fitzgerald

Archive | 1986

Logic-circuit layout for large-scale integrated circuits

Joseph Michael Fitzgerald; Pho Hoang Nguyen; Robert Russell Williams

Archive | 1986

LSI circuits adaptable for custom design methods

Anthony Gus Aipperspach; Joseph Michael Fitzgerald

Archive | 1985

Multi-function FET masterslice cell

Joseph Michael Fitzgerald

Archive | 1989

Porous circuit macro for semiconductor integrated circuits

Anthony Gus Aipperspach; Dennis Thomas Cox; Joseph Michael Fitzgerald

Archive | 1984

Semiconductor static read/write memory having an additional read-only capability

Anthony Gus Aipperspach; Joseph Michael Fitzgerald; Philip T. Wu

Archive | 1984

Combined read-only and read/write memory and method of accessing the same

Anthony Gus Aipperspach; Joseph Michael Fitzgerald; Philip T. Wu

Archive | 1983

Master slice semiconductor chip having a new multi-function FET cell

Joseph Michael Fitzgerald

Archive | 1988

Makro-Struktur und Verfahren zum Herstellen von Makros für VLSI-Halbleiterschaltungen. Macro-structure and method of manufacturing of macros for VLSI semiconductor circuits.

Anthony Gus Aipperspach; Douglas M. Dewanz; Joseph Michael Fitzgerald

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Anthony Gus Aipperspach

IBM

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Robert Russell Williams

IBM

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Douglas M. Dewanz

IBM

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Philip T. Wu

IBM

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Pho Hoang Nguyen

IBM

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Dennis Thomas Cox

IBM

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