Anthony Gus Aipperspach

A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

A 64 b PowerPC RISC microprocessor is incorporated in a 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors and next into a silicon-on-insulator (SOI) version of the same technology. Some architectural changes improve CPI, including doubling the L1 instruction and data caches to 128 kB and adding a 256 kB L2 directory. The total transistor count increased from 12 M to 34 M.

A commercial multithreaded RISC processor

Implementation of a coarse-grained hardware-multithreaded processor for use in the IBM AS1400 uses a PowerPC architecture that supports two threads. Hardware multithreading is a technique for tolerating memory latency by utilizing otherwise idle cycles in the CPU. This requires the replication of the processor architecture registers for each thread. Replication is not required for the majority of processor logic such as instruction cache, data cache, TLB, instruction fetch and dispatch mechanisms, branch units, fixed-point units, floating-point units, and storage-control units.

A 180-ps, 220 K-circuit Bicmos Asic Logic Chip

A 12.7-mm BiCMOS ASIC logic chip with 0.5-pm devices and four levels of metal has a,n extensive I/O and internal circuit library and RAM miscro compilers. CMOS, BiNMOS, and BiCMOS circuit!; are available for optimization of either density or performance, and a chip timing scheme supports intermixing of the circuit types. A wired density of 220K-circuits is achieved. The chip features a central clock receiver and low resistance on the I/O lines.