Joseph P. Donnelly

Employing Step-and-Flash imprint lithography for gate-level patterning of a MOSFET device

Step and Flash Imprint Lithography (SFIL) is an alternative lithography technique that enables patterning of sub-100 nm features at a cost that has the potential to be substantially lower than either conventional projection lithography or proposed next generation lithography techniques. SFIL is a molding process that transfers the topography of a rigid transparent template using a low-viscosity, UV-curable organosilicon solution at room temperature and with minimal applied pressure. Employing SFIL technology we have successfully patterned areas of high and low density, semi-dense and isolated lines down to 20 nm, and demonstrated the capability of layer-to-layer alignment. We have also confirmed the use of SFIL to produce functional optical devices including a micropolarizer array consisting of orthogonal 100 nm titanium lines and spaces fabricated using a metal lift-off process. This paper presents a demonstration of the SFIL technique for the patterning of the gate level in a functional MOSFET device.

Thin germanium-carbon alloy layers grown directly on silicon for metal-oxide-semiconductor device applications

We report the growth and characterization of thin (<35nm) germanium-carbon alloy (Ge1−xCx) layers grown directly on Si by ultrahigh-vacuum chemical vapor deposition, with capacitance-voltage and leakage characteristics of the first high-κ/metal gate metal-oxide-semiconductor (MOS) capacitors fabricated on Ge1−xCx. The Ge1−xCx layers have an average C concentration of approximately 1at.% and were obtained using the reaction of CH3GeH3 and GeH4 at a deposition pressure of 5mTorr and growth temperature of 450°C. The Ge1−xCx films were characterized by secondary ion mass spectrometry, atomic force microscopy, x-ray diffraction, and cross-sectional transmission electron microscopy. A modified etch pit technique was used to calculate the threading dislocation density. The x-ray diffraction results showed that the Ge1−xCx layers were partially relaxed. The fabricated MOS capacitors exhibited well-behaved electrical characteristics, demonstrating the feasibility of Ge1−xCx layers on Si for future high-carrier-mob...

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.

Negative Differential Resistance in Buried-Channel

We study the device characteristics of Si-capped Ge_xC_1-x pMOSFETs from room temperature down to 77 K. The output characteristics of these devices reveal a negative differential resistance (NDR) at temperatures below 150 K. Our measurements indicate a higher effective carrier mobility in the buried-channel Ge_xC_1-x with respect to the Si-reference sample, which suggests that the observed NDR is due to real-space transfer of hot holes from the higher mobility Ge_xC_1-x channel layer into the lower mobility Si cap layer.

\hbox{Ge}_{x} \hbox{C}_{1 - x}

This work presents the effects of Si-cap thickness and temperature on device performance of buried channel Si/Ge1−xCx/Si p-MOSFETs. The silicon-cap thickness (3–9 nm), as well as the operating temperature (300 K down to 77 K), plays a significant role on device performance in terms of drive current, sub-threshold slope, effective hole mobility and Ion–Ioff ratio. The 7 nm Si-capped device demonstrates highest mobility enhancement because of reduced remote Coulomb scattering. In addition, the valence band offset between the Si-cap/Ge1−xCx interface was quantitatively extracted by fitting the stair-case behavior of split C–V characteristics with self-consistent simulations of one-dimensional Poisson and Schrodinger equations.

pMOSFETs

Summary form only given. In this work we investigated vertical flash memory devices with Al2O3 as control oxide with protein mediated self assembled PbSe nanocrystals used as floating gate. The introduction of high-k dielectric as control oxide provides lower voltage/faster operation and hence less power consumption compared with the devices fabricated with SiO2 as control oxide. For appropriate memory operation the dielectric permittivity, conduction/valence band offset and thickness of the high-k material have to be properly engineered. Higher permittivity ensures better capacitance and scalability; higher band offset improves retention and programming window. Al2O3 has the potential to be the high-k replacement of inter-poly oxide due to its relatively high electron and hole barrier heights and high permittivity.

Effects of Si-cap thickness and temperature on device performance of Si/Ge1?xCx/Si p-MOSFETs

We report the growth and characterization of thin germanium-carbon layers grown directly on Si (111) by ultra high-vacuum chemical vapor deposition. The thickness of the films studied is 8-20 nm. The incorporation of small amount (less than 0.5%) of carbon facilitates 2D growth of high quality Ge crystals grown directly on Si (111) without the need of a buffer layer. The Ge 1−x C x layers were grown in ultra high vacuum chemical vapor deposition chamber, at a typical pressure of 50 mTorr and at a growth temperature of 440 °C. CH 3 GeH 3 and GeH 4 gases were used as the precursors for the epitaxial growth. The Ge 1−x C x films were characterized by atomic force microscopy (AFM), secondary ion mass spectroscopy, x-ray diffraction, cross-sectional transmission electron microscopy and Raman spectroscopy. The AFM rms roughness of Ge 1−x C x grown directly on Si (111) is only 0.34 nm, which is by far the lowest rms roughness of Ge films grown directly on Si (111). The dependence of growth rate and rms roughness of the films on temperature, C incorporation and deposition pressure was studied. In Ge, (111) surface orientation has the highest electron mobility; however, compressive strain in Ge degrades electron mobility. The technique of C incorporation leads to a low defect density Ge layer on Si (111), well above the critical thickness. Hence high quality crystalline layer of Ge directly on Si (111) can be achieved without compressive strain. The fabricated MOS capacitors exhibit well-behaved electrical characteristics. Thus demonstrate the feasibility of Ge 1−x C x layers on Si (111) for future high-carrier-mobility MOS devices that take advantage of high electron mobility in Ge (111).

Vertical Flash memory devices with Protein-assembled Nanocrystal floating gate and A1 2 O 3 control oxide

Conventional scaling of bulk CMOS devices appears to have been stymied in recent years, leading to a flurry of activity in multi-gate and enhanced channel mobility MOSFETs With the advent of low leakage and low equivalent oxide thickness (EOT) high-k gate dielectrics, the limitation of Ge MOSFETs of not having a stable high-quality native gate oxide, has been mitigated and high mobility Ge channel MOSFETs have been demonstrated. Additionally, the lower band gap of Ge with the higher mobility should increase carrier injection from the source to the channel above that of Si. However, bulk Ge MOSFETs are limited by Ge substrates which are more expensive, fragile and have worse thermal conductivity than Si. Germanium channel MOSFETs fabricated on a Si substrate, incorporate the Ge channel either on a thick relaxed Si1-xGex buffer layer or a strained Ge-on-insulator (SGOI) substrate, followed by a pure Ge epi layer. However such schemes are expensive and require complex processing. In this talk, we will discuss various schemes to circumvent some of these limitations. In one approach, Ge channels comparable to the inversion layer thickness were grown directly on Si substrates using a low temperature (~370o C) ultra high vacuumchemical vapor deposition (UHV-CVD). This technique requires neither an expensive starting substrate nor complex thick relaxed buffer layers. Thin (~15nm) compressivelystrained selective epitaxial grown (SEG) Ge film were achieved on small open Si active areas by ultra high vacuum-chemical vapor deposition (UHV-CVD). It was subsequently capped with a hafnium oxide gate dielectric at room temperature and then annealed. SEG growth and capping the Ge layers prior to thermal processing improve the stability of the layers, and the roughness of the epitaxial films. The compressively-strained Ge PMOSFETs show a ~2X enhancements in drive current compared to Si devices. In other approaches, we have used thin, strained Ge buffer layers with rapidly varying Ge mole fractions to deflect threading dislocations away from the top Ge epitaxial layer. In yet another scheme, we have grown Ge:C partially strain compensated epitaxial films on Si in order to increase the allowable thermal budgets for MOSFET fabrication, and demonstrated enhanced hole mobilities in pMOSFETs compared to Si devices.

A comprehensive study of growth techniques and characterization of epitaxial Ge1-xCx (111) layers grown directly on Si (111) for MOS applications

High-k/metal gate pMOSFETs were fabricated on high-quality Ge_1-xC_x for the first time. Ge_1-xC_x layers with very low RMS roughness of ~3Aring were grown directly on Si by ultra-high-vacuum chemical vapor deposition (UHVCVD), without the use of relaxed Si_1-xGe_x virtual substrates. Ge_1-xC_x buried-channel (BC) and surface-channel (SC) pMOSFETs with EOT = 1.9 nm and L = 10 mum exhibited high drive currents of 10.8 and 15.2 muA/mum, respectively, for V_GS-V_T = -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2times enhancement in I_Dsat and 1.6times enhancement in the transconductance (G _m). The corresponding enhancements for the SC devices were 3times and 2times, respectively. These results represented an effective hole mobility enhancement of ~1.5times for the BC devices and ~2.5times for the SC devices over the universal curve for Si