Sagnik Dey

Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier

The authors have fabricated a nonvolatile flash-memory device using SiGe nanocrystal floating gate with new variable oxide thickness (VARIOT) tunnel barrier. It is found that the writing speed of VARIOT sample is almost hundred times faster at a low programming voltage of 5-8 V compared to the traditional flash memory with single-layer tunnel barrier. The results have shown that a long-charge retention time of up to 106 s and a good endurance characteristics of up to 106 write/erase cycles can be achieved at 85 degC

Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention

We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F 2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 degC. The cell shows a large memory window of ~1 V and endurance of more than 105 cycles

Improved hot-electron reliability in strained-Si nMOS

Strained-Si/relaxed-Si/sub 1-x/Ge/sub x/ structures provide a viable means of improving CMOS performance. For nMOS devices, the tensile strain in pseudomorphic Si on relaxed-Si/sub 1-x/Ge/sub x/ splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced intervalley scattering. In this paper, in addition to confirming enhanced performance for biaxial-strained-Si nMOS, we present hot-electron degradation characteristics for the first time, showing improvement over bulk Si.

Molecular-beam epitaxy growth of device-compatible GaAs on silicon substrates with thin (∼80nm) Si1−xGex step-graded buffer layers for high-κ III-V metal-oxide-semiconductor field effect transistor applications

The authors report the fabrication of TaN–HfO2–GaAs metal-oxide-semiconductor capacitors on silicon substrates. GaAs was grown by migration-enhanced epitaxy (MEE) on Si substrates using an ∼80-nm-thick Si1−xGex step-graded buffer layer, which was grown by ultrahigh vacuum chemical vapor deposition. The MEE growth temperatures for GaAs were 375 and 400°C, with GaAs layer thicknesses of 15 and 30nm. We observed an optimal MEE growth condition at 400°C using a 30nm GaAs layer. Growth temperatures in excess of 400°C resulted in semiconductor surfaces rougher than 1nm rms, which were unsuitable for the subsequent deposition of a 6.5-nm-thick HfO2 gate dielectric. A minimum GaAs thickness of 30nm was necessary to obtain reasonable capacitance-voltage (C-V) characteristics from the GaAs layers grown on Si substrates. To improve the interface properties between HfO2 and GaAs, a thin 1.5nm Ge interfacial layer was grown by molecular-beam epitaxy in situ after the GaAs growth. The Ge-passivated GaAs samples were th...

Thin germanium-carbon alloy layers grown directly on silicon for metal-oxide-semiconductor device applications

We report the growth and characterization of thin (<35nm) germanium-carbon alloy (Ge1−xCx) layers grown directly on Si by ultrahigh-vacuum chemical vapor deposition, with capacitance-voltage and leakage characteristics of the first high-κ/metal gate metal-oxide-semiconductor (MOS) capacitors fabricated on Ge1−xCx. The Ge1−xCx layers have an average C concentration of approximately 1at.% and were obtained using the reaction of CH3GeH3 and GeH4 at a deposition pressure of 5mTorr and growth temperature of 450°C. The Ge1−xCx films were characterized by secondary ion mass spectrometry, atomic force microscopy, x-ray diffraction, and cross-sectional transmission electron microscopy. A modified etch pit technique was used to calculate the threading dislocation density. The x-ray diffraction results showed that the Ge1−xCx layers were partially relaxed. The fabricated MOS capacitors exhibited well-behaved electrical characteristics, demonstrating the feasibility of Ge1−xCx layers on Si for future high-carrier-mob...

Design, fabrication, testing and simulation of porous silicon based smart MEMS pressure sensor

Porous silicon based piezoresistive pressure sensor has been designed, fabricated and tested in the range of 0 to 1 bar and temperature range of 20/spl deg/C to 80/spl deg/C. A suitable signal conditioning analog circuit consisting of constant current generator and an offset adjustable low noise instrumentation amplifier has been designed and tested. The analog output is then digitized through an ADC and fed to FPGA. Architecture for compensation of nonlinear temperature dependence of pressure sensor has been implemented and tested in FPGA. A device model of porous silicon pressure sensor has also been developed with a view to realize a SMART pressure sensor.

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.

Low-frequency noise in SiGeC-based pMOSFETs

The SiGeC ternary alloy seems to be an attractive material system for Si-based device applications, because the incorporation of a small amount of C in the high-mobility SiGe layer offers an additional degree of freedom for tuning the bandgap, band offsets and the lattice strain in group IV heterostructures. In this work, detailed low-frequency noise (LFN) results in SiGeC pMOSFETs are presented. Our experimental results in saturation regime of the SiGe MOSFET show that the noise in SiGeC MOSFETs at gate bias |VGS-VT|<0.4V can be referred to the gate terminal as a noise voltage SVG=VG2, which implies (ΔN) fluctuation with correlated noise in the cap and SiGeC channel currents. Overall, the trend shows that the gate referred noise voltage scales inversely with the gate area, and that the variation of the noise level has log-normal distribution. Therefore, the noise in SiGeC MOSFETs can be expressed as S=Savg*exp(t*σNp), where t=±1,...,±3 is a coefficient selected for desired confidence probability of 0.6,...,0.99 respectively, and σ is the standard deviation of the log-normal distribution of the noise level around its average Savg, later given by (ΔN-Δμ) fluctuation in the cap layer and SiGeC channel of pMOSFET.

Considerations for evaluating hot-electron reliability of strained Si n-channel MOSFETs

Abstract Tensile-strained Si on relaxed Si 1− x Ge x buffers has emerged as an important channel material for improving CMOS performance. The ability of tensile-strained Si to dramatically improve MOSFET drive currents has received much attention in the literature in recent years, but little is known about its reliability characteristics. In this review we discuss some of the issues that should be considered in the analysis of hot-electron reliability of strained Si n-channel MOSFETs.

3X hole mobility enhancement in epitaxially grown SiGe PMOSFETs on (110) Si substrates with high k / metal gate for hybrid orientation technology

MOSFETs were fabricated on both thick and thin epi SiGe films. An ultra thin (~ 1- 2 nm) epi Si cap grown on the SiGe layers serves to separate the Ge from the high k dielectric as well as form a SiO2 interfacial layer between the SiGe channel and the high k gate dielectric. There is evidence that this cap layer is completely oxidized during the ozone based ALD high k deposition process. Both epitaxial Si as well as SiO2 based capping layers are reported to improve the interface for pure Ge devices. PMOSFETs were fabricated using a conventional 4 mask step process flow using a deposited field isolation oxide, ALD high k, metal gate electrode and implanted source/drain regions.