Sachin Joshi

Improved Ge Surface Passivation With Ultrathin

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm²middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

\hbox{SiO}_{X}

Germanium interactions are studied on HfO2 surfaces, which are prepared through physical vapor deposition (PVD) and by atomic layer deposition. X-ray photoelectron spectroscopy and temperature-programed desorption are used to follow the reactions of germanium on HfO2. Germanium chemical vapor deposition at 870 K on HfO2 produces a GeOx adhesion layer, followed by growth of semiconducting Ge0. PVD of 0.7 ML Ge (accomplished by thermally cracking GeH4 over a hot filament) also produces an initial GeOx layer, which is stable up to 800 K. PVD above 2.0 ML deposits semiconducting Ge0. Temperature programed desorption experiments of ∼1.0ML Ge from HfO2 at 400–1100 K show GeH4 desorption below 600 K and GeO desorption above 850 K. These results are compared to Ge on SiO2 where GeO desorption is seen at 550 K. Exploiting the different reactivity of Ge on HfO2 and SiO2 allows a kinetically driven patterning scheme for high-density Ge nanoparticle growth on HfO2 surfaces that is demonstrated.

Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

The authors report the fabrication of TaN–HfO2–GaAs metal-oxide-semiconductor capacitors on silicon substrates. GaAs was grown by migration-enhanced epitaxy (MEE) on Si substrates using an ∼80-nm-thick Si1−xGex step-graded buffer layer, which was grown by ultrahigh vacuum chemical vapor deposition. The MEE growth temperatures for GaAs were 375 and 400°C, with GaAs layer thicknesses of 15 and 30nm. We observed an optimal MEE growth condition at 400°C using a 30nm GaAs layer. Growth temperatures in excess of 400°C resulted in semiconductor surfaces rougher than 1nm rms, which were unsuitable for the subsequent deposition of a 6.5-nm-thick HfO2 gate dielectric. A minimum GaAs thickness of 30nm was necessary to obtain reasonable capacitance-voltage (C-V) characteristics from the GaAs layers grown on Si substrates. To improve the interface properties between HfO2 and GaAs, a thin 1.5nm Ge interfacial layer was grown by molecular-beam epitaxy in situ after the GaAs growth. The Ge-passivated GaAs samples were th...

Ge interactions on HfO2 surfaces and kinetically driven patterning of Ge nanocrystals on HfO2

We report the growth and characterization of thin (<35nm) germanium-carbon alloy (Ge1−xCx) layers grown directly on Si by ultrahigh-vacuum chemical vapor deposition, with capacitance-voltage and leakage characteristics of the first high-κ/metal gate metal-oxide-semiconductor (MOS) capacitors fabricated on Ge1−xCx. The Ge1−xCx layers have an average C concentration of approximately 1at.% and were obtained using the reaction of CH3GeH3 and GeH4 at a deposition pressure of 5mTorr and growth temperature of 450°C. The Ge1−xCx films were characterized by secondary ion mass spectrometry, atomic force microscopy, x-ray diffraction, and cross-sectional transmission electron microscopy. A modified etch pit technique was used to calculate the threading dislocation density. The x-ray diffraction results showed that the Ge1−xCx layers were partially relaxed. The fabricated MOS capacitors exhibited well-behaved electrical characteristics, demonstrating the feasibility of Ge1−xCx layers on Si for future high-carrier-mob...

Molecular-beam epitaxy growth of device-compatible GaAs on silicon substrates with thin (∼80nm) Si1−xGex step-graded buffer layers for high-κ III-V metal-oxide-semiconductor field effect transistor applications

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.

Thin germanium-carbon alloy layers grown directly on silicon for metal-oxide-semiconductor device applications

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for p-channel metal oxide semiconductor devices fabricated on alternative substrate orientations. This letter reports on the experimental observation and density functional theory (DFT) based theoretical prediction of a valence band offset between the (100) and (110) silicon surfaces directly bonded to each other. This constitutes a different type of junction created by the presence of two different surface orientations in close proximity to each other and not by doping or material variations. Experimentally, this band offset was observed as an asymmetry in the forward and reverse current-voltage characteristics of a two terminal device designed to flow a current across the DSB interface. Further, the valence band offset obtained from DFT simulations was used in a conventional device simulator (TAURUS-MEDICI) to simulate the behavior of this struc...

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.

Theoretical and experimental investigation of valence band offsets for direct silicon bond hybrid orientation technology

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

MOSFETs were fabricated on both thick and thin epi SiGe films. An ultra thin (~ 1- 2 nm) epi Si cap grown on the SiGe layers serves to separate the Ge from the high k dielectric as well as form a SiO2 interfacial layer between the SiGe channel and the high k gate dielectric. There is evidence that this cap layer is completely oxidized during the ozone based ALD high k deposition process. Both epitaxial Si as well as SiO2 based capping layers are reported to improve the interface for pure Ge devices. PMOSFETs were fabricated using a conventional 4 mask step process flow using a deposited field isolation oxide, ALD high k, metal gate electrode and implanted source/drain regions.

Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for PMOS devices that are fabricated on alternative substrate orientations. Significantly higher leakage was observed for P+/N diodes if the junction depletion region was located close to the interface between the (110) and (100) Si surfaces. Hydrogen and fluorine passivation of this interface by ion implantation resulted in an order of magnitude improvement in the reverse leakage. In this brief, the experiments that performed using several dose levels of H2, F, and N implants are described. Electrical characterization data for reverse leakage, forward current, and ideality factors are presented in the form of cumulative probability plots, from which it is concluded that H and F passivation by ion implantation consistently provides a significant improvement in junction leakage, as compared to an unimplanted DSB wafer. An increase in the forward resistance was observed due to the implants, as compared to bulk Si (100) control samples.