Joseph P. Lorenzo

Simulation studies of silicon electro‐optic waveguide devices

Several silicon‐on‐insulator guided‐wave structures have been analyzed as potential electro‐optic waveguide modulators using the pisces‐ii two‐dimensional (2D) device simulation program. From the electron and hole concentration data, the 2D refractive index profile is obtained. The profile is then spatially averaged with respect to a 2D cosine representation of the guided‐wave E field to obtain the effective modal index changes at 1.3 and 1.55 μm. The channel‐waveguide devices studied include the metal‐oxide‐semiconductor (MOS) diode, and the one or two‐gate metal‐oxide‐semiconductor field‐effect transistor (MOSFET) with single‐or double‐transverse injection. The single‐gate double‐injection MOSFET modulator offers the most promise with 10−3 refractive index changes possible, changes comparable in size to the Pockels effect in LiNbO3 or GaAs.

Optical waveguiding in a single-crystal layer of germanium silicon grown on silicon

Low-loss waveguiding at lambda = 1.3 microm has been observed in a partially strained, 10-microm-thick, single-crystal layer of Ge(0.1)Si(0.9) grown by chemical-vapor deposition upon an intrinsic (100) silicon substrate. The TM-mode propagation loss in the multimode planar guide was 1.9 dB/cm.

Integration of magneto-optical garnet films by metal-organic chemical vapor deposition

This paper presents a novel technique for integrating yttrium iron garnets, namely Ce:YIG, onto semiconductor platforms using metal-organic chemical vapor deposition (MOCVD). Large amounts of cerium (Ce) could be incorporated into the garnet structure because of the nonequilibrium nature of the technique. The method can alloy up to 54% Ce, thereby increasing the refractive index and enhancing the Faraday rotation of the YIG films. Faraday rotations as high as 0.4/spl deg///spl mu/m at 1.3 /spl mu/m were achieved in MOCVD-grown garnets, exceeding the rotations of bismuth-doped YIG films (0.15/spl deg///spl mu/m at 1.3 /spl mu/m) grown by liquid-phase epitaxy. The easy axis of magnetization is within the plane of the films. When the garnet films were sputtered onto [100] magnesia (MgO) buffer layers, their hysteresis loops indicated that they were isotropic.

Indium phosphide passivation using thin layers of cadmium sulfide

The electrical properties of the silicon dioxide/n‐type (100) InP interface were significantly improved by thin interlayers of chemical bath deposited CdS. The CdS layer and CdS/InP interface were investigated with x‐ray photoelectron spectroscopy (XPS) and photoluminescence (PL). XPS data showed reduction of native oxides and the prevention of subsequent substrate oxide growth following CdS layer deposition. PL spectra, measured between 1.0 and 1.3 μm, indicate a reduction in phosphorus vacancies. Metal–insulator–semiconductor (MIS) capacitors fabricated with CdS‐treated InP substrates displayed interface‐state densities below 1×1011 eV−1 cm−2 when determined from the difference between the high‐ and low‐frequency capacitance data.

Silicon double‐injection electro‐optic modulator with junction gate control

Novel structures for carrier‐induced electro‐optical phase modulation in crystalline silicon are examined. A new dual‐injection field‐effect transistor structure for guided‐wave light modulation at 1.3 μm is proposed and analyzed. It consists of an elongated cathode‐anode‐gate structure integrated in a rib waveguide. Dual‐gate and single‐gate control are considered. The overlap between the plasma charge density and the optical guided mode is computed. For a cathode‐anode voltage of 0.32 V, the effective refractive index of the waveguide mode changes by ΔN=1×10−3 when the gate voltage is altered by 12 V. Numerical estimates of the bias current, pinchoff voltage, interaction length, and modulator speed are given.

Analysis of thin CdS layers on InP for improved metal–insulator–semiconductor devices

Cadmium sulfide (CdS) layers were deposited from an aqueous solution of thiourea, cadmium sulfate, and ammonia on (100) n‐InP at 60–95 °C. X‐ray photoelectron spectroscopy showed that the deposition process effectively removes native oxides on InP and forms a protective layer for subsequent dielectric deposition. Surface analysis also showed that the InP surface is not P deficient following oxide deposition on CdS‐treated InP. Capacitance–voltage and conductance–voltage measurements of metal–insulator–semiconductor (MIS) capacitors were used to compare samples with and without CdS films between InP and a deposited insulator. Capacitance–voltage response of CdS‐treated MIS structures showed well‐defined regions of accumulation, depletion, and inversion. The interface‐state density at midgap was reduced from 5×1011 to 6×1010 eV−1 cm−2 with CdS treatment. Depletion‐mode MIS field‐effect transistors made using this new passivation technique exhibited superior device performance to that of untreated samples.

Optimization of Chemical Bath‐Deposited Cadmium Sulfide on InP Using a Novel Sulfur Pretreatment

A thiourea/ammonia pretreatment followed by chemical bath deposition of cadmium sulfide was used to passivate the surface of indium phosphide (100). The pretreatment was shown by X‐ray photoelectron spectroscopy to effectively remove native oxides from the InP surface and form an indium sulfide layer. The subsequent chemical bath deposition of CdS on a sulfur‐passivated surface forms a stable layer that protects the substrate from oxidation during chemical vapor deposition of . The passivation process was optimized for electrical response by varying the reactant concentrations of the chemical bath. Reflection high‐energy electron‐diffraction (RHEED) analysis showed that the pretreatment results in a (1 × 1) surface, which reconstructs to (2 × 1) after heating in vacuo to 200°C. RHEED and atomic force microscopy showed an increase in CdS surface roughness with increasing thickness corresponding to the formation of oriented surface asperities. CdS‐passivated metal‐insulator‐semiconductor diodes exhibited a density of interface states of when calculated by the high‐low method, more than one order of magnitude lower than the of untreated metal‐insulator‐semiconductor samples. A CdS layer thickness of ~ 10 A was determined to yield optimal capacitance‐voltage response for all CdS deposition conditions investigated.

Cadmium sulfide surface stabilization for InP-based optoelectronic devices

Thin layers of chemical bath deposited cadmium sulfide were used to improve the surface and interface properties of InP and its latticed-matched III-V compounds. X-ray photoelectron spectroscopy indicates chemical reduction of surface oxides and the prevention of subsequent group III or V oxide formation. Photoluminescence spectra, measured between 1.0 and 1.3 μm, indicate a dramatic reduction in phosphorus vacancies following CdS treatment. Metalinsulator-semiconductor capacitors fabricated onn-type InP substrates with CdS interlayers display near-ideal quasi-static response and interface-state densities in the low 1011/eVcm2 range. Thin CdS layers were used to passivate the surface of InAlAs/InGaAs high electron mobility transistors (HEMTs) and metal-semiconductor-metal (MSM)photodetectors.AfterCdS treatment, Schottky diode barrier heights of 0.6 eV were regularly obtained. For HEMTs, drain-togate current ratios of 8 × 104 were observed after CdS treatment. For a new backside illuminated MSM design, the dark current of CdS-treated samples was reduced three orders of magnitude to below 1 nA.

High-performance InGaAs-InP APDs on GaAs

Epitaxial layer transfer was used to fabricate In/sub 0.53/Ga/sub 0.47/As-InP avalanche photodiodes on GaAs substrates. The photodiodes displayed a gain-bandwidth product of 80 GHz, dark current of 10.20 nA at 90% of the breakdown voltage, and responsivity of 5.9 A/W at 2 V below breakdown. Performance is comparable to standard devices fabricated on InP substrates, suggesting the transfer process does not degrade material quality.

Low‐temperature chemical vapor deposition of SiO2 at 2–10 Torr

We discuss a new low‐pressure and low‐temperature process for the chemical vapor deposition (CVD) of silicon dioxide. The process differs from conventional low‐pressure CVD in that lower temperatures (150–300 °C) and a unique pressure window (2–10 Torr) provide the conditions for the reaction of silane (SiH4) and oxygen. In this thermal process, activation energies of 0.15–0.18 eV and deposition rates of 100 A/min at 250 °C are achieved. This technique is approximately 15 times less sensitive to the O2:SiH4 ratio than atmospheric pressure CVD. The deposition conditions are compatible with both low‐temperature silicon and III‐V technologies. Preliminary current‐voltage and capacitance‐voltage measurements on Si indicate dielectric field strength of 3–8×106 V/cm and fixed oxide charge density (Qss) less than 1011 cm−2.