Josip Zilak

Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost

A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18-μm CMOS, together with high-speed HCBT with BVCEO = 3.6 V and double-emitter HCBT with BVCEO = 12 V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks.

Optimization of Horizontal Current Bipolar Transistor (HCBT) technology parameters for linearity in RF mixer

Double-balanced active mixer based on a Gilbert cell is designed and fabricated as the first RF circuit in Horizontal Current Bipolar Transistor (HCBT) technology. The maximum IIP3 of 17.7 dBm at mixer current of 9.2 mA and conversion gain of -5 dB are achieved. Three different HCBT structures are used in a mixer design to examine the effect of process parameters on mixer linearity. The main effect on the linearity has the n-collector doping profile since it governs the onset of Kirk effect. The improvement of 6 dB in IIP3 can be achieved by using the optimum HCBT structure, if switching quad transistors operate at or near the high current region. The circuit model parameters of three HCBT structures are extracted, accurately reproducing the measured device and circuit data.

Impact of emitter interface treatment on the horizontal current bipolar transistor (HCBT) characteristics and RF circuit performance

The impact of the HF cleaning step prior to the emitter α-Si deposition on the Horizontal Current Bipolar Transistor (HCBT) electrical characteristics is analyzed A longer HF dip results in a thinner emitter interface oxide implying a smaller emitter resistance (Re), which equals 85Ω for the unit HCBT as compared to 104 Ω for the unit HCBT with a shorter HF dip. The thinner oxide is still sufficiently thick to block the emitter α-Si etching and protect the intrinsic transistor structure. The impact of the emitter interface properties on the performance of designed high-linearity double-balanced active mixers is examined. The reduction of the emitter resistance results in 1.8 dB higher conversion gain and 2.4 dB lower IIP3 at 50 mA for the mixer without degeneration emitter resistor (RE). The effect of interface oxide thickness is shown to be negligible for RE>10 Ω. The HCBT mixers achieve maximum IIP3 of 23.8 dBm and conversion gain of 2.4 dB at the current of 50 mA.

Reliability Degradation Mechanisms of Horizontal Current Bipolar Transistor

The impact of the reverse-bias emitter-base stress and the mixed-mode stress on horizontal current bipolar transistor (HCBT) reliability characteristics is analyzed. Under the stress conditions, hot carriers are generated and injected toward silicon-oxide interfaces above and below HCBTs emitter n+ polysilicon region where the traps responsible for the base current and beta (β) degradations are formed. Different degradation rates of three HCBT structures measured under both stresses suggest various contributions of the top and bottom oxides to total damage. A larger contribution of the top interface under the reverse-bias emitter-base stress and of the bottom interface under the mixed-mode stress is determined. A lower doping concentration in the bottom part of the intrinsic transistor and a shorter emitter polysilicon predeposition oxide etching both reduce the generation of interface traps during stress tests. The time-dependent trap degradation simulations are run on the structures with the realistic doping profiles to explain the measured stress data on various HCBT structures.

Impact of the local p-well substrate parameters on the electrical performance of the Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor

Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor is analyzed by the device simulations. Geometrical parameters of the local p-well substrate, which is used to introduce the second drift region are investigated. It is shown that the length of the p-well lpw=0.5 µm is sufficient to obtain efficient electric field shielding and BVCEO independent of the transistor current gain. The analysis of the distance between the extrinsic base and the p-well region (dpw) shows that the optimum dpw exists. The optimum structure with lpw=0.5 µm and dpw=0.6 µm has BVCEO=30 V and ƒT=7 GHz. With assumed p-well mask misalignment tolerances, a good trade-off between BVCEO and ƒT is achieved with transistors having the ƒT·BVCEO at the Johnsons limit.

Fully-integrated voltage controlled oscillator in low-cost HCBT technology

Design of cross-coupled voltage controlled oscillator in low-cost HCBT technology is presented. Beside the low-complexity front-end devices, only 2 metal layers are used and the passives are implemented in the available on-chip structures. Varactors are fabricated as pn-junctions by using the ion implantation from the technology. Symmetric inductors are fabricated by using the topmost metal layer. Since only 2 aluminum metal layers are available, small thickness of the aluminum layer and proximity of the silicon substrate limit the inductor quality factor. Varactor and inductor models for circuit simulations are developed by using the device and electromagnetic simulations, respectively, and are compared to measured characteristics of fabricated devices.

Investigation of double-emitter reduced-surface-field horizontal current bipolar transistor breakdown mechanisms

Breakdown behavior of double-emitter reduced-surface-field horizontal current bipolar transistor is extensively analyzed by measurements and 3D device simulations. By the addition of the 2nd drift region, BVCEO of double-emitter structure is improved from 12 V up to 36 V and can be tuned by the length of the drift region. By increasing the length of the drift region, positive feedback loop of the common-emitter soft-breakdown can be completely broken making the BVCEO independent on transistor current gain. Transistors with BVCEO and BVCBO equal to the collector-substrate breakdown voltage are demonstrated. We also report that base current reversal in forced-VBE measurement does not occur and cannot be used for accurate determination of BVCEO of analyzed structures.

Analysis of hot carrier-induced degradation of Horizontal Current Bipolar Transistor (HCBT)

The relative contribution of the hot electrons and hot holes to the reliability degradation of the Horizontal Current Bipolar Transistor (HCBT) is investigated by TCAD simulations. The base current (IB) degradation, obtained by the reverse-bias emitter-base (EB) and mixed-mode stress measurements, is caused by a hot carrier-induced interface trap generation at silicon-oxide interfaces above and below HCBTs emitter n+ polysilicon region. The simulation analysis is performed on the HCBT structures with different n-collector doping profiles and n-hill silicon sidewall surface treatment. The used lucky electron injection model distinguishes the hot carrier type responsible for the damage and makes it possible to predict the HCBT reliability behavior. It is shown that the majority of traps under the reverse-bias EB stress is located at the top interface and is caused by the hot holes, whereas the hot electrons produce the traps under the mixed-mode stress, located mostly at the bottom interface.

Improving the horizontal current bipolar transistor breakdown voltage by floating field plates

A method for improvement of breakdown voltage of the Horizontal Current Bipolar Transistor (HCBT) by application of floating field plates (FFPs) is presented. The FFPs are used for shaping of the potential distribution and the electric field in the base-collector depletion region. The BVCEo improvement from 13 V to 25 V by the addition of one FFP to a double-emitter HCBT is demonstrated by measurements of fabricated devices. The FFP is fabricated by the extrinsic base implantation and is aligned to the extrinsic base, allowing for ideal control of the electric field shaping. New structure is added to the HCBT BiCMOS process flow at zero-cost. Simulations show that multiple FFPs can be used for the increase of the BVceo in discrete steps. BVCEO of 44 V is achieved by using 5 FFPs.

Impact of the emitter length scaling on electrical characteristics of horizontal current bipolar transistor with single polysilicon region

Emitter length scaling of HCBT with single polysilicon region is investigated by 3D device simulations with the emphasis on the high frequency characteristics. It is shown that collector current and junction capacitances have linear dependence on the emitter length. Collector resistance can be represented by two components which appear in parallel, one that scales proportionally with the emitter length and a constant part which describes lateral portion of the extrinsic transistor. Cut-off frequency is improved for small emitter area devices due to current spreading in the collector region which reduces the current density and causes the base push-out at higher collector currents. The effect cannot be captured by scalable transistor model and separate set of model parameters is needed for transistors with very small emitter size.