Marko Koricic

Horizontal Current Bipolar Transistor With a Single Polysilicon Region for Improved High-Frequency Performance of BiCMOS ICs

A new horizontal current bipolar transistor (HCBT) with a single polysilicon region and a CMOS gate polysilicon near the n⁺ emitter region is integrated with CMOS technology with the addition of two or three masks (three or four masking steps) and a small number of additional fabrication steps. The single-poly HCBT with an optimized collector exhibits f_T and f_max of 51 and 61 GHz, respectively, and an f_TBV_CEO product of 173 GHz · V, which are the best reported HCBT characteristics to date and among the highest performance Si BJTs. An HCBT with only two additional masks to CMOS has f_T and f_max of 43 and 53 GHz, respectively, and an f_TSV_CEO product of 120 GHz · V. The developed innovative fabrication techniques enable a very low-cost BiCMOS platform for wireless communication circuits.

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The substrate is used for HCBT fabrication utilizing crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.

Collector region design and optimization in Horizontal Current Bipolar Transistor (HCBT)

Three different types of the n-collector region of Horizontal Current Bipolar Transistor (HCBT) are analyzed and compared. The optimum n-collector profile suppresses the charge sharing effect between the intrinsic and extrinsic base regions, resulting in the uniform base width and electric field in the intrinsic transistor. This implies a maximum BVCEO and an optimum fTBVCEO product among compared structures. The HCBT with a selectively implanted collector (SIC) is introduced and examined. It reduces RC and increases fT comparing to the other n-collector designs. The analyses give the guidelines for the optimum HCBT design for targeted applications.

Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost

A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18-μm CMOS, together with high-speed HCBT with BVCEO = 3.6 V and double-emitter HCBT with BVCEO = 12 V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks.

Horizontal Current Bipolar Transistor (HCBT) for the low-cost BiCMOS technology

A new Horizontal Current Bipolar Transistor (HCBT) is developed and integrated with a commercial 0.18 µm CMOS technology resulting in a very low-cost BiCMOS technology suitable for wireless applications. The number of fabrication steps is significantly reduced in comparison to conventional vertical-current bipolar transistors. The optimum HCBT performance can be achieved by 3 additional masks to CMOS process while an even simpler version with 2 additional masks is also demonstrated. The integration of HCBT with bulk CMOS is achieved by introducing innovative process steps such as protecting the active transistor region during polysilicon etching by low-resistance native oxide, placement of high-doped emitter and collector regions in oxide trenches etc. The compact HCBT structure has small junction capacitances and fT and fmax of 34 GHz and 45 GHz, respectively, with BVCEO=3.4 V.

Double-Emitter HCBT Structure—A High-Voltage Bipolar Transistor for BiCMOS Integration

Fabrication of a novel high-voltage double-emitter horizontal current bipolar transistor (HCBT) structure integrated with the standard 0.18-μm CMOS and high-speed HCBT is presented. The device takes advantage of 3-D collector charge sharing to achieve full depletion of the intrinsic collector region and to limit the electric field at the base-collector junction. Transistors with BVCEO = 12.6 V, fT ·BVCEO = 160 GHz·V , and β·VA = 28 700 V are demonstrated. The device is fabricated in HCBT BiCMOS process flow without the use of additional lithography masks and represents a zero-cost solution for integration of a high-voltage bipolar device.

Optimization of Horizontal Current Bipolar Transistor (HCBT) technology parameters for linearity in RF mixer

Double-balanced active mixer based on a Gilbert cell is designed and fabricated as the first RF circuit in Horizontal Current Bipolar Transistor (HCBT) technology. The maximum IIP3 of 17.7 dBm at mixer current of 9.2 mA and conversion gain of -5 dB are achieved. Three different HCBT structures are used in a mixer design to examine the effect of process parameters on mixer linearity. The main effect on the linearity has the n-collector doping profile since it governs the onset of Kirk effect. The improvement of 6 dB in IIP3 can be achieved by using the optimum HCBT structure, if switching quad transistors operate at or near the high current region. The circuit model parameters of three HCBT structures are extracted, accurately reproducing the measured device and circuit data.

Impact of emitter interface treatment on the horizontal current bipolar transistor (HCBT) characteristics and RF circuit performance

The impact of the HF cleaning step prior to the emitter α-Si deposition on the Horizontal Current Bipolar Transistor (HCBT) electrical characteristics is analyzed A longer HF dip results in a thinner emitter interface oxide implying a smaller emitter resistance (Re), which equals 85Ω for the unit HCBT as compared to 104 Ω for the unit HCBT with a shorter HF dip. The thinner oxide is still sufficiently thick to block the emitter α-Si etching and protect the intrinsic transistor structure. The impact of the emitter interface properties on the performance of designed high-linearity double-balanced active mixers is examined. The reduction of the emitter resistance results in 1.8 dB higher conversion gain and 2.4 dB lower IIP3 at 50 mA for the mixer without degeneration emitter resistor (RE). The effect of interface oxide thickness is shown to be negligible for RE>10 Ω. The HCBT mixers achieve maximum IIP3 of 23.8 dBm and conversion gain of 2.4 dB at the current of 50 mA.

Examination of novel high-voltage double-emitter horizontal current bipolar transistor (HCBT)

Electrical characteristics of a novel high-voltage double-emitter HCBT structure integrated with the standard 180 nm bulk CMOS are presented. 3D collector charge sharing is used to achieve intrinsic base shielding and to limit the electric field across the intrinsic base-collector junction. This is accomplished by the transistor layout i.e. the mask design. Transistors with BVCEO =12.6 V, VA=301 V and fT=12.7 GHz are fabricated in a standard HCBT BiCMOS process flow without the use of the additional lithography masks. Physical behavior of the transistor is thoroughly examined by 3D device simulations.

Examination of Horizontal Current Bipolar Transistor (HCBT) Reliability Characteristics

The reliability characteristics of HCBT are examined for the first time by employing reverse emitter-base (EB) and mixed-mode stresses. Three HCBT structures with different n-collector doping profiles and different oxide etching parameters before polysilicon deposition are measured, exhibiting different behavior at each stress test. Due to the specific HCBT structure, the traps generation causing IB degradation, occurs at different regions, i.e. at EB pn-junction near both the top and the bottom EB oxide for reverse EB stress and only at the bottom EB oxide for mixed-mode stress, as discovered by TCAD simulations. Pre-deposition oxide etching conditions turned out to be critical for IB degradation after reverse EB stress, whereas the n-collector vertical doping profile mostly impacts the trap generation after the mixed-mode stress. The 1/f noise characteristics also show the highest degradation for HCBT structures with the highest stress damage.