John Richard E. Hizon

Dual core capability of a 32-bit DLX microprocessor

We report an implementation of a 32-bit DLX microprocessor capable of operating in a dual core environment. The processor was modified for it to be capable of operating atomic instructions, a requirement in a dual core environment. The dual core environment was simulated using a similar core acting as a pseudo slave core. The resulting processor can then be interfaced with another instance of the same processor to function as a dual core processor. It can also be interfaced with a DSP co-processor that is compatible with the handshaking protocols of the processor. The resulting implementation yielded a power reduction of 17.9% (due to a more efficient register file) and an area overhead of 23% (due to additional blocks needed for dual core capability) compared to previous DLX implementations of the laboratory.

Comparison of classical and fuzzy control in active mass damping of a flexible structure using acceleration feedback

Most research on fuzzy control claim that fuzzy controllers outperformed classical controllers. In this study, classical and fuzzy controllers are compared in the control of a flexible structure employing an active mass damper system using acceleration feedback. Both controllers are optimized and evaluated using Matlab and implemented in real-time using real-time workshop. The parameters of both controllers are tuned to achieve minimum sum-of-squares of the top floor acceleration. The controllers are evaluated based on the rate of convergence and performance criterion.

An aggressive power optimization of the ARM9-based core using RAZOR

With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental noise. On the other hand, as long as all errors can be detected and recovered, a considerable amount of energy can be saved. In this paper, a processor based on the ARM architecture was first implemented and verified, and then the RAZOR technique was integrated to add resiliency. The core with and without RAZOR are then simulated using an FFT program at different supply voltages and clock frequencies. The optimized core achieved a maximum energy reduction of 22% at constant clock frequency, while a 23% performance increase is observed at constant energy consumption.

High-level implementation of an ARM7 microprocessor with multicore capabilities

This paper presents an implemention of an ARM7 microprocessor with multicore capabilities. The required modifications to support multiprocessing include: the addition of atomic instructions to the instruction set and the addition of a bus interface. The implementation resulted to a 170% power overhead and a decrease in area by 61% compared with the single core implementation of the ARM7 microprocessor in the laboratory. The maximum allowable frequency attained was 17 MHz, an improvement from the previous implementations 10 MHz.

Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-V th devices

Supply voltage scaling greatly reduces the power consumption of circuits and is typically used in applications with loose speed constraints but tight power budgets. However, without digital standard cell libraries characterized at low voltages, integration of this technique is difficult in the semi-custom design flow. Thus, digital circuits are synthesized at the nominal voltage and their operating frequency is estimated at low voltages. However, this existing approach does not guarantee the timing of circuits containing standard cells with multiple threshold voltages whose delays scale differently as the supply voltage decreases. Slow high Vth non-critical paths are at risk of becoming critical paths at lower voltages that can cause timing errors. A new framework for timing analysis and removal of violating paths is then proposed for dual-Vth circuits. The framework is integrated in a 65nm CMOS digital flow and is verified using an 8-bit microcontroller core as the input design. The method successfully eliminated violating paths but the 35%-61% delay margin of the standard cell libraries contributed to the delay estimation errors.

Monolithic Spiral Inductors for a 0.25 μm Digital CMOS Process

The digital CMOS processes currently enjoys a continued scaling in feature sizes. This allows the the process to have transitors that are viable to be used for RF circuits. This has fueled a lot of research focused on using CMOS technology to implement RF circuits. Inductors are present in most of the RF circuit modules and oftentimes consume large areas on silicon. However, the lack of models that will accurately predict their behavior on silicon using a CMOS process presents a major limitation in the full integration of RF systems on CMOS. These inductors are characterized using an inductor model to effectively compare the merits of each implementation and to identify relevant parasitics that limit the performance of these inductors.

Integrating spiral inductors on 0.25 /spl mu/m epitaxial CMOS process

In this study, different spiral inductor implementations are compared. Q enhancement techniques are also evaluated in minimizing inductor losses on a 0.25 /spl mu/m epitaxial CMOS process. Inductor coupling between adjacent inductors was also considered in this study by measuring the S/sub 21/ parameter between the inductors implemented. Reported structures that minimize inductor coupling and layout strategies are explored in reducing coupling. From measured results, octagonal spiral inductors have higher Qs compared to square spirals. Results from the study have shown that patterned ground shields not only improve inductor Q but also limit inductor coupling. In integrating multiple inductors, a diagonal configuration improves isolation by at least 5 dB when compared to a horizontal configuration.

A modified class of Seok ultra-low power voltage references for wireless sensor nodes

With the emergence of energy-starved systems like wireless sensor nodes, it becomes much more of a necessity for important blocks in such systems like the voltage reference (VR) to work at an ultra-low power consumption. Furthermore, the varying requirements of the functional blocks of a wireless sensor node (WSN) entail varying VR requirements, therefore flexibility in the design of VRs is required. This work proposes a novel replica approach for reducing error in stacked 2-transistor (2T) topology proposed by Seok, allowing integration of low-power, low-error, and scalable VRs in WSNs. The proposed design achieved a 140× improvement in the TC while obtaining a 3× reduction in the power consumption for the 4T variant.

A reconfigurable FGMOS based OTA-C filter

A novel low voltage reconfigurable FGMOS OTA is proposed that allows the manipulation of the OTAs input capacitance for wider tuning without additional power consumption. Schematic simulations using the AMS 0.35μm CMOS process with a VDD=1.8V, show a minimum DR of 69dB is achieved with capacitance tuning and at least 63dB with current bias tuning using at least 29.4μW of power. When used in a third order Butterworth filter, the reconfigurable OTA contributed to a wide tuning range from 240kHz-3.8MHz. Filter DR of 63.6dB was achieved at a maximum power of 3.8mW.

An ultra low-voltage standard cell library in 65-nm CMOS process technology

In this paper, the design of an ultra-low voltage standard cell library is discussed. This includes the design constraints in designing each gate on a schematic level as well as techniques used in designing the layout. The method of performing timing and power characterization of the standard cell library and how the logical and physical library files are generated are discussed. The accuracy of the standard cell library is then verified through the use of several test circuits.