Joyashree Bag

Design and VLSI implementation of a robot navigation processor deploying CORDIC based anti-collision algorithm with RFID technology

Design of a multiplier-less Robot navigation processor with anti-collision and Coordinate Rotation Digital Computer (CORDIC) based algorithm has been presented. The processor, deploying low power wireless Radio Frequency Identification Detection (RFID) technology has been implemented as an efficient VLSI architecture. The hardware of the processor has been realized up to RTL schematic level and fits into a single chip. Xilinx ISE 14.3 design simulation tool and KINTEX-7 FPGA kit have been used for implementation purpose. The performance of the proposed processor has been compared with the existing processor and it reveals improvement in terms of speed, hardware requirement and delay.

Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation

ABSTRACT In the present work, a power efficient differential phase shift keying (DPSK) modem has been implemented using COordinate Rotation DIgital Computer (CORDIC) algorithm in hardware descriptive language (VHDL) code. Here, CORDIC algorithms are used to generate the carrier in the modulator and to implement the multiplier in the demodulator. Carrier generator on the same chip minimizes the effect of noise significantly. Single-chip implementation provides a low power DPSK modem operating with high frequency which is suitable for wireless communication system. The CORDIC algorithm based DPSK modem is found to be a much efficient system in terms of reduced hardware cost, improved performance, and included flexibility. Importance of portable field programmable gate array (FPGA) based device for wireless communication system and system on single chip is now growing rapidly. In this context, the proposed modem provides an efficient alternative over conventional DPSK modem. Real-time verification is performed using Kintex-7 FPGA board. The performance of the proposed modem has been compared with a normal DPSK modem implemented in software defined radio kit using Xilinx block and Spartan-6 FPGA.

VLSI Implementation of a Key Distribution Server Based Data Security Scheme for RFID System

RFID Technology is now a globally accepted technology which is rapidly emerging in every field of science and applications. Its excellent feature of very fast auto-identification without line of sight has made it popular in different areas of wire-less communication based system. But, during data transmission/exchange, security of personal or confidential data, it exposes serious threats to the security and privacy of individuals and organizations. Data security for RFID technology is now a mandatory condition to be provided by the manufacturer for better customer support and services. In this paper, we have proposed a security scheme which introduces a trusted Key management system. In this system, not a single key but several keys will be maintained, controlled and provided by the Key distribution server system (KDSS). It will be extremely useful for military persons in remote places where it is useful to identify specific item or guide to right route. Data will be encrypted using different programmable cellular automata (PCA) rules which is also provided with the key by the server. The system processor has been implemented up to RTL schematic level using Xilinx ISE14.3 simulation tool and virtex-7 FPGA board for real time verification of its functionality.

Power efficient anti-collision algorithm for RFID technology with added data security feature and its implementation in VHDL

In the field of RFID technology, a power efficient tag anti-collision protocol plays an important role in the entire system based on this technology. The query Tree scheme is one of the most important anti-collision protocols for RFID technology. Researchers have developed different Query algorithm with improved features, each time reducing the number of query iteration and idle slots. The EPC Gen protocol uses this anti-collision algorithm, which is popularly known and globally accepted for its secured data transmission feature but having a huge load of data itself. Low power design and implementation of the anti-collision protocol is another challenging area for cost effective RFID system. In our research work, we have implemented the protocol as low power single chip solution. Furthermore, we have included a data security scheme in this protocol for secured data transmission. VHDL code has been used for design purpose, Xilinx ISE 14.3 simulation tools to simulate the design and Kintex-7 FPGA board for implementation purpose. We have also implemented other anti-collision protocols with different bit size and a comparative study of performance evaluation has been provided.

Development and VLSI implementation of a data security scheme for RFID system using programmable cellular automata

Data security is a critical issue for Radio Frequency Identification (RFID) system as it hides important information within it. From both technical and business points of view, it is vital to ensure the security of data for the worldwide use of RFID technology, otherwise hacker or attacker can control the data transmission. So, to secure the RFID tag from ‘hacking’, a data security scheme for RFID tags based on programmable cellular automata has been proposed and implemented in this article. The processor for the system and the secret code generator have been designed in Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using programmable cellular automata (PCA). The processor and ID generator have been simulated in Xilinx ISE 14.3 simulation tools and have implemented the design up to RTL schematic level and the processor has been emulated on the Kintex-7 FPGA board for verification in real environment.

Design and VLSI implementation of power efficient processor for object localisation in large WSN

The presence of multiple obstacles on the real deployed geographical area may hinder the effective operations of large scale wireless sensor network in terms of significant disturbance in proper routing, increased delay in data transmission and increased energy consumptions. To overcome this problem, a novel pulse mode object localisation algorithm and its VLSI implementation for designing the sensor node processor is proposed in this article. The algorithm supports distributed and energy efficient sleep scheduling with periodic synchronisation and reconfigure the routing scheme that can be used to extend the life time of sensor network. The algorithm is made power efficient by using pulse mode operation. It is a high performance sensor node processor with an overall power consumption of 0.012 mW in active mode with a dynamic current of 1.27 mA at the working frequency of 1,536 MHz. The algorithm is verified using MATLAB for different possible obstacles and percentage error has been calculated for each case. The hardware of this sensor node processor has been realised using ISE 14.3 simulation tools and emulated in Virtex-V prototype field programmable gate array kit.

Designing a micro-heater with Genetic Algorithm based optimized parameters and study its performance

The basic aim of this work is to predict the optimum values of the system parameters of a micro-heater and to design the micro-heater with those optimized parameters. The parameter optimization is done by employing the Genetic Algorithm to get a better micro-heater having the features of consuming minimum power, reasonable size and of attaining the desired temperature at least time. The performance of the micro-heater designed with the optimized parameters is studied using simulation software (Intelsuit v8.2).