Pranab Kishore Dutta

Design and implementation of an asynchronous arbiter circuit using SET CMOS hybrid architecture approach

This paper demonstrates a CMOS Single electron transistor (SET) hybrid arbiter circuit which will act like a communication switch between multiple resources. The proposed architecture combines the merits of CMOS and SET to give a more efficient and compact nanometer scale circuit. The designed arbiter circuit utilizes the Coulomb blockade oscillation characteristics of SET to give better performances in terms of circuit area, power dissipation and delay. MIB compact model and BSIM4.6 model is used to design the circuit and the functionality of the result is verified by Tanner spice simulator.

Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation

ABSTRACT In the present work, a power efficient differential phase shift keying (DPSK) modem has been implemented using COordinate Rotation DIgital Computer (CORDIC) algorithm in hardware descriptive language (VHDL) code. Here, CORDIC algorithms are used to generate the carrier in the modulator and to implement the multiplier in the demodulator. Carrier generator on the same chip minimizes the effect of noise significantly. Single-chip implementation provides a low power DPSK modem operating with high frequency which is suitable for wireless communication system. The CORDIC algorithm based DPSK modem is found to be a much efficient system in terms of reduced hardware cost, improved performance, and included flexibility. Importance of portable field programmable gate array (FPGA) based device for wireless communication system and system on single chip is now growing rapidly. In this context, the proposed modem provides an efficient alternative over conventional DPSK modem. Real-time verification is performed using Kintex-7 FPGA board. The performance of the proposed modem has been compared with a normal DPSK modem implemented in software defined radio kit using Xilinx block and Spartan-6 FPGA.

Error probability independent delay analysis of single electronics circuits

Summary This study based on Poisson process and orthodox theory of single electron tunneling for the first time proposes an error probability independent delay model for delay calculation of single electronics circuits, involving multiple tunneling events. The Poisson process assumes that the tunneling events are independent of each other, but in real single electronics circuits they are correlated through space and time, so this effect has been considered and included in the proposed model. The dependence of tunneling rates on the logic transition is thoroughly investigated. Finally, the model is applied to different logic gates, and the result is compared with the well known Monte Carlo approach to prove the accuracy of the proposed model.

Design and implementation of 4-bit ripple carry adder using SETMOS architecture

Adder circuit is one of the basic building block of digital data processing circuits. Performance of a digital processing system can be improved by designing high performance adder circuit. Replacing the conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology by hybrid approach of Single Electron Transistor (SET) and MOSFET technology will enhance the overall performance of the system. A hybrid approach of SET and MOSFET can take the advantage of both the technologies and improve the performance of the circuit. The paper presents the design of 4 bit Ripple Carry Adder (RCA) using SET-MOS hybrid approach. The circuit is implemented using MIB model and a BSIM 4.6 model and the result is verified using Tenner spice simulator.

Quantum confinement effects in the subthreshold characteristics of short-channel DMDG MOSFET

In this paper, 2D Poissons equation and 1D Schrödinger equation have been solved self-consistently to derive the analytical model of subthreshold current and subthreshold slope for DMDG SON MOSFET in sub 20 nm regime. Extensive study has been carried out to examine the behavior of subthreshold slope with the variation of different parameters like channel length, Si film thickness and doping concentration. It is found that the subthreshold slope in the proposed model have a near ideal value for a given Si film thickness and substrate doping concentration for channel length as short as 20nm.

Influence of mole fraction variation of binary metal gate on SON MOSFET device performance

Work function engineering with continuous horizontal mole fraction variation in a binary metal alloy gate has been proposed already on silicon on nothing (SON) MOSFET. Presently, concept of work function engineering by mole fraction variation along both vertical as well as horizontal direction in a binary alloy gate is applied analytically in our model. Effects of this vertical mole fraction variation on various device parameters such as threshold voltage, drain current, transconductance, drain conductance and voltage gain are studied and compared with the model suggested by Manna et al. and an improvement of overall performance has been observed.

A Quantum Analytical Model for Inversion Current in Short Channel DMDG SON MOSFET

DMDG MOSFET, a promising alternative to conventional CMOS devices, has evolved from extensive research in the present era. In our present work we have incorporated quantum mechanical effects on DMDG SON MOSFET because these effects became significant factors in deca-nanometer scale. Here, we have studied the current voltage characteristics of DMDG SON MOSFET incorporating the quantum mechanical effects. For maximum charge inversion in the channel, minimum value of surface potential is considered to calculate charge and corresponding current along the channel.

Design and VLSI implementation of power efficient processor for object localisation in large WSN

The presence of multiple obstacles on the real deployed geographical area may hinder the effective operations of large scale wireless sensor network in terms of significant disturbance in proper routing, increased delay in data transmission and increased energy consumptions. To overcome this problem, a novel pulse mode object localisation algorithm and its VLSI implementation for designing the sensor node processor is proposed in this article. The algorithm supports distributed and energy efficient sleep scheduling with periodic synchronisation and reconfigure the routing scheme that can be used to extend the life time of sensor network. The algorithm is made power efficient by using pulse mode operation. It is a high performance sensor node processor with an overall power consumption of 0.012 mW in active mode with a dynamic current of 1.27 mA at the working frequency of 1,536 MHz. The algorithm is verified using MATLAB for different possible obstacles and percentage error has been calculated for each case. The hardware of this sensor node processor has been realised using ISE 14.3 simulation tools and emulated in Virtex-V prototype field programmable gate array kit.

Small - signal parameter extraction to study the RF performance of SOI and SON MOSFET

A simple small-signal equivalent circuit for generalized horizontal SOI and SON MOSFET has been presented. The intrinsic parameters of the small-signal model are obtained from a compact capacitance based analytical model Using those small-signal model parameters, frequency dependent performances of those structures are simulated with SILVACO SMART SPICE RF Module. It has been realized that SON technology improves the frequency response due to improved conductance and reduced parasitic effects. This type of combined analytical and simulation approach allows us to predict the technology road map for future ultra dense, low power nanoelectronics devices and their efficiency in RF frequency range.

A Comparative Study for Disease Identification from Heart Auscultation using FFT, Cepstrum and DCT Correlation Coefficients

We present a comparative study for correlation coefficients of three different, but popular transforms of audio signals i.e. Fast Fourier Transform (FFT), Cepstrum and Discrete Cosine Transform (DCT). But this study is done keeping into mind an important application, the heart sound analysis or heart auscultation analysis which manually is done by doctors for disease identification. We present a very simple automated software based approach for first detecting whether the heart is normal or abnormal and then identifying the disease if within the range of diseases for which it has been trained. Here our application has been trained for only three heart diseases, Mitral Regurgitation, Mitral Stenosis, and Splits. Further training might enable our application for identifying other diseases as well. We get better the detection accuracy with the increase of training data. We have taken the help of FBS (Frontiers in Bioscience) online data base for heart sounds for this purpose, and have used their .wav format of heart sound files for our analysis. But along with these we also found out that though Cepstrum is a very important transform for speaker recognition and other audio based application, but here in case of heart sound analysis it is not very user friendly for analysis.