Ju Hwan Yi

Exploiting intellectual properties in ASIP designs for embedded DSP software

The growing requirements on the correct design of a high-performance system in a short time force us to use IPs in many designs. In this paper, we propose a new approach to select the optimal set of IPs and interfaces to make the application program meet the performance constraints in ASIP designs. The proposed approach selects IPs with considering interfaces and supports concurrent execution of parts of task in kernel as software code with others in IPs, while the previous state-of-the-art approaches do not consider IPs and interfaces simultaneously and cannot support the concurrent execution. The experimental results on real applications show that the proposed approach is effective in making application programs meet the performance constraints using IPs.

Technology mapping for storage elements based on BDD matching

Most digital systems have storage elements such as flip-flops and latches of various kinds. So when we synthesize from an RT level description, we must choose proper storage elements from the cell library. In this paper, we propose an extended version of a BDD which facilitates describing the behavior of these storage elements and a new technology mapping method for storage elements based on the proposed BDD.

Multiple behavior module synthesis based on selective groupings

In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented the previous methods scheduled each of them sequentially, and implemented them as a single module. Though the method Is appropriate for sharing the functional units, it ignored the following two aspects: (1) different interconnection patterns among DFGs can increase the interconnection area and delay of the critical path, (2) the sequential scheduling of DFGs has a difficulty in considering the effects on the other DFGs not scheduled yet. We show an efficient way to solve the problems using a selective grouping method and the extensions of the traditional scheduling methods. The experimentation reveals that the result obtained by the proposed method is better to reduce interconnection area and to meet the timing constraints than those obtained by the previous methods.

Estimation of inertial-delay dependent switching activities by using time-stamped transition density

We propose a new method to improve the accuracy of the transition density for the estimation of inertial-delay dependent switching activities in combinational circuits. The previous methods have used the same technique that is commonly used in logic simulators to filter out unacceptably short logic pulses. However, they underestimated the difference between probabilistic property of the transition density and the deterministic property of signals in logic simulations. We, for the first time in our knowledge, describe the problems of the previous methods and propose a new method to overcome them. It is based on the time-stamped transition density and a new formula considering inertial-delay effect in the probabilistic domain. The experimental results demonstrate the validity of our proposed method.

SYMBOLIC REACHABILITY ANALYSIS FOR MULTIPLE-CLOCK SYSTEM DESIGN

This paper proposes a symbolic reachability analysis method for multiple-clock system design, which is the first approach to deal with both synchronization problems caused by metastability and rate mismatch problems caused by clock frequency mismatches in a single framework. Three methods are described to reproduce problems that occur with multiple-clock system design during reachability analysis: (1) alternate evaluation for a system with two clocks as the base-line model, (2) nondeterministic delayed evaluation to reproduce a synchronization problem, and (3) double evaluation to reproduce a clock frequency mismatch. Experimental results on ISCAS 89 benchmark show an improvement factor of average CPU time as compared to Clarkes method by 1.29, 55.41, 2.19 and 45.23 times when alternate evaluation, double evaluation, alternate evaluation with NDDE and double evaluation with NDDE is applied, respectively.