Wooseung Yang

Communication-efficient hardware acceleration for fast functional simulation

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.

Multi-thread VLIW processor architecture for HDTV decoding

This paper describes a single-chip high definition television (HDTV) decoder which performs system parsing, video decoding, audio decoding and resolution conversion. To process a huge amount of data and deal with various standards in the decoder, a multi-thread processor architecture is proposed to minimize the overhead cycles of task-switching. The features of parallelism and conditional branches in MPEG2 video decoding algorithm are considered to enhance the performance of the embedded processor and to reduce the size of code memory. Experimental results show that the proposed processor architecture is 5.3 times faster than a scalar processor at the cost of negligible increase of code memory.

Current status and challenges of SoC verification for embedded systems market

The SoC has become an indispensable solution in the embedded systems market. This tutorial introduces todays main issues of SoC design with a focus on the verification solutions proposed by EDA vendors and SoC developers. After the SoC platform based on several embedded cores is fixed, design efforts are focused on the verification of peripheral IPs and debugging of the software in the context of the platform. For IP verification, formal methods are first used when applicable and suitable to statically remove design bugs and improve coverage, and test-bench automation tools are applied to test the IP with realistic test vectors. Finally, all the IPs are mapped in FPGA in the emulator, to be verified in the real operating environment. For integrated system verification, the emulation environment is set up as soon as the platform is selected and the block-level partitioning is done. A well-established emulation platform helps progressive refinement of newly added SoC components and early development and verification of the software.

A new RTL debugging methodology in FPGA-based verification platform

In this paper we present a new RTL debugging methodology in FPGA-based verification platform. This method provides internal node probing in the co-simulation environment. Full observability is guaranteed using 32-bit scan module generated automatically. Most commercial debugging tools are limited to hundreds of internal nodes for the observability in the co-simulation. The proposed method increases the observability of design to 100%. Debugging feature named in RTL gives the benefits that designers feel more comfortable in RTL than in gate level since the signal names in gate level are complicated and incomprehensive. Designers can control the depth of probing in the design hierarchy. The overheads of area and time due to improving the design observability are turned to be small for a reasonable number of internal node probing.

Low-power high-level synthesis using latches

High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping clock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39 ~ 65% reduction in power consumption within almost same area compared to the conventional power management scheme using clock gating.

Automatic generation of software/hardware co-emulation interface for transaction-level communication

This paper presents a methodology for generating interface of a co-emulation system where processor and emulator execute testbench and design unit, respectively while interacting with each other. To reduce the communication time between the processor and emulator, data transfers are performed in transaction level instead of signal level. To do this, transactor should be located near the DUT mapped on the hardware emulator. Consequently transactor is described in a synthesizable way. Moreover, the transactor design depends on both emulator system protocol and DUT protocol. Therefore, transactor description would not only be time-consuming but also error-prone task. Based on the layered architecture, we propose an automated procedure for generating co-emulation interface from platform-independent transactor. We have also discussed about the practical issues on multiple channel and clock skew problem.

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and accelerator at every simulation time, which results in poor performance by splitting transactions on the simulator-to-accelerator channel into pieces. Occasional synchronization with predictions and recoveries makes it possible to merge multiple transfers yielding substantial performance gain compared to the conventional method.

A multi-threading MPEG processor with variable issue modes

MPEG decoding chips have to support multiple features such as video stream decoding, transport stream parsing, multi-standard support, scan line conversion for on-screen display, and audio/video synchronization. Some of these features are computation-intensive, while others are size-intensive. In this paper an embedded processor specialized for the MPEG decoding is proposed to cope with the complicated requirements. The proposed processor can execute up to four operations at a time to handle intensive computation, and can change instruction issue rate according to the required performance in order to save code size which is very important in MPEG applications. In addition, the processor can switch tasks rapidly to keep the number of buffers existing between tasks minimal.

Soc Prototyping and Verification

Verification of System-On-a-Chip (SoC) poses us a serious challenge as it involves not only high chip complexity but also hardware/software co-verification along with short design time-to-market. Traditional IC design verification technologies based on simulation, emulation, and prototyping often fall short of meeting this challenge of SoC verification. This chapter starts with an introduction of SoC design verification flow. To reduce the time-to-market it is crucial to provide the system-level model for each hardware block, software component and communication channel in the very early stage of the SoC design process. It can be best addressed by performing the so-called ‘soft prototyping.’ System-level modeling using SystemC is explained as it is expected to be widely employed as a reference model. Software part of the SoC is run on Instruction Set Simulation (ISS), which is interfaced to hardware models described in either software (like HDL or SystemC) or physical hardware. We explained the hybrid SoC design verification technique which incorporates both simulation and prototyping in a single verification environment to maximally exploit the merits of both approaches. Simulation acceleration and emulation are explained followed by the introduction of HW/SW co-simulation and FPGA-based co-emulation techniques. These techniques based on initial system-level modeling of high-level abstract behavior followed by gradual refinement and verification by comparing with the reference model, enables fast and error-free SoC design closure

CONSCEP: A CONFIGURABLE SoC EMULATION PLATFORM FOR C-BASED FAST PROTOTYPING

FPGA-based emulation, which is now widely used in the design and verification of System-on-a-Chip (SoC), is applicable only when the RTL design for the whole system is available, thus resulting in a long design turn-around time. In this paper, we present a new design flow based on a C-to-hardware IMPLEmentation tool (CIMPLE) and a CONfigurable SoC Emulation Platform (CONSCEP) that emulates the on-chip bus system prior to the RTL design of each SoC component. With the emulation environment set up in the early stage of the design process, the design and verification task of each functional block in the SoC can be performed not only faster, but also more complete as a more complete set of test vectors can be applied before the integration. CONSCEP consists of (1) configurable bus components for the given on-chip bus standard and (2) a set of transactors to link the HDL models of the pre-verified IP blocks with the C models for the behavioral blocks to be designed, or software blocks. CIMPLE translates the C model for a hardware module to a SystemC code, which can be synthesized and directly attached to the CONSCEP as an IP. CIMPLE allows global variables, nested function calls, and simple pointer access, which significantly reduces the code migration. The proposed design flow is demonstrated using a JPEG encoder/decoder system and successfully applied to a commercial MPEG4 video codec chip.