Juan Boon Tan

Study of TDDB reliability in misaligned via chain structures

The low-k time-dependent dielectric breakdown (TDDB) mechanisms in misaligned via chain structures are studied. The results show that for small and medium inline misalignments, the spacing reduction effect due to via protrusion dominates the variations of failure time distribution, and sqrt-E model can describe the correlation with good accuracy. In the case of larger misalignments, two process related early failure mechanisms have been found. One leakage path is the via bottom discontinuous and hollow area due to via misalignment caused etch-through into bottom dielectrics, and the other mode is related to excess remaining residues generated in the misaligned structure which are difficult to be to completely removed without robust wet clean process. Process optimization approach like the modified multiple-step post etch wet clean has been demonstrated to improve the weakness effectively.

Foundry TSV integration and manufacturing challenges

Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.

Effect of via arrangement on electromigration performance

Despite the theory of electromigration is well understood, it is still none trivial to meet all the qualification requirements as technology scales. This paper addresses the impacts of via configuration on electromigration from both physical and statistical point of view.

Integration challenges of low temperature BEOL interconnects

We present the first exploratory low temperature, lower than standard back-end-of-line (BEOL) interconnects temperature in CMOS. The approach poses several challenges such as undercut in pad via, photo resist residue defects post Aluminum (Al) etch and patch defects post passivation etch. We achieved the electrical targets and met reliability specifications of passivation integrity test (PIT), stress migration (SM), electro migration (EM) for high aspect ratio (HAR) dual damascene via, and pad via interconnects.

A Study of unique galvanic failure due to interaction with well structure

In this paper, a thorough investigation on a memory yield detractor due to metal void is presented. The metal void was found to have a strong dependency on isolated well size. It was formed due to galvanic effect. The failure mechanism in this unique case was found due to a potential developed from charges on the wafer surface and opposing charges trapped in the well. The post-etch solvent acted as the electrolyte and caused copper to migrate. This study includes a few counter-measures to address the issue.

SRAM V MIN yield challenge in 40nm embedded NVM process

Embedded non-volatile memory (NVM) introduces additional thermal processes to a logic process flow and the impact from this extra thermal budget becomes more considerable with continued device scaling. This paper investigates the mechanism of SRAM VMIN degradation in a 40nm embedded NVM process and provides a solution to address the degradation caused. Failure analysis shows enlarged poly grain size for SRAM PMOS due to the NVM thermal processes, resulting in a large shift in threshold voltage. The results show that introduction of a p-poly boron pre-dope greatly helps to recover the SRAM VMIN. The mechanism for the VMIN recovery is also explained, with further high-temperature SRAM VMIN studies showing the effectiveness of p-poly pre-dope even at elevated temperatures.

Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications

This paper successfully demonstrates a functional and reliable self-aligned, split-gate NVM cell, down to a very competitive and small cell size. This NVM cell is embedded into a 40 nm Low Power (LP) ground rule logic process with copper low-K interconnects. The self- alignment sequence with gate spacer and poly CMP (Chemical Mechanical Polishing) provides an optimized and small cell that can be easily integrated in the standard logic process, in a modular way. This is the first time that the industry has demonstrated a functional split-gate embedded Flash memory cell at 1.1V VDD. This embedded Flash process also yielded on a baseline 32 Mb high-density SRAM test chip as well as a 10% larger automotive-grade embedded Flash cell. We have further demonstrated reliability data that met the tightest market requirements, with a more relaxed 55 nm ground rule on a 16 Mb test array, using the same 40 nm LP process.

2.5D packaging solution — From concept to platform qualification

Silicon interposers offer a viable path to perpetuating the trend of increased chip performance per die area, as projected by Moores law, which can no longer be met by simply shrinking feature sizes. The enablement of such packaging solutions not only requires new processes for Through Silicon Vias (TSV), thin die manufacturing, assembly and test, but also a well-defined concept of process and supply chain. In a joint work between GLOBALFOUNDRIES and Amkor Technology, a test vehicle with focus on processing aspects and chip package interaction (CPI) has been designed, manufactured, tested, and stressed. The findings and data have been used for the definition of a common interposer platform, now available for customers. This paper describes the design and manufacturing concept of the test vehicle, discusses challenges for interposer processing and test, and shares reliability results.

Impact of pattern density on copper interconnects barrier metal liner integrity

The dependency of Cu interconnects barrier metal liner integrity due to neighboring pattern density is presented in this paper. It was found that TaN/Ta bi-layer barrier metal liner on isolated Cu interconnects was oxidized through electrical test and failure analysis. An elaborate study on the neighboring interconnects pattern density as well as process solutions were explored to investigate the impacts on the metal liner. Hypotheses were discussed. Results showed that there is an obvious pattern density correlation with the integrity of the metal liner. A comprehensive methodology was devised to check the process window of the metal liner process. The deduction is care needs to be taken in the design of interconnects circuitry. While metal liner process can be optimized, a balance is needed to ensure a robust and reliable barrier metal with neighboring interconnects pattern density.

Wire bonding, bumping & assembly related failures & improvements

In this paper, investigation of wire bonding, bumping and assembly related failures are performed using optical microscopy, secondary electron microscopy and transmission electron microscopy. Also, the understandings of the failures and root causes are presented. For example, corrosions caused by contaminant such as Fluorine and Cu precipitates on Al-Cu alloyed bond pads that lead to discolored or non-stick on pads problem are discussed. In addition, the formation of small bumps when oxide/silicon nitride passivation is employed and chipping at die edges caused during assembly that leads to open-circuit are studied. In conclusion, possible solutions of these failures are recommended to achieve robust assembly and packaging.