Soh Yun Siah

Study of TDDB reliability in misaligned via chain structures

The low-k time-dependent dielectric breakdown (TDDB) mechanisms in misaligned via chain structures are studied. The results show that for small and medium inline misalignments, the spacing reduction effect due to via protrusion dominates the variations of failure time distribution, and sqrt-E model can describe the correlation with good accuracy. In the case of larger misalignments, two process related early failure mechanisms have been found. One leakage path is the via bottom discontinuous and hollow area due to via misalignment caused etch-through into bottom dielectrics, and the other mode is related to excess remaining residues generated in the misaligned structure which are difficult to be to completely removed without robust wet clean process. Process optimization approach like the modified multiple-step post etch wet clean has been demonstrated to improve the weakness effectively.

Foundry TSV integration and manufacturing challenges

Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.

40nm Embedded Self-Aligned Split-Gate Flash Technology for High-Density Automotive Microcontrollers

This paper successfully demonstrates a logic- compatible, high performance and high reliability, automotive-grade 2.5V embedded NVM process extending over several generations. A high-density flash macro is used to debug process complexities which arise from the add-on modules. The modular approach is adopted for integrating self-aligned, floating-gate-based split-gate SuperFlash® ESF3 cell into 40nm CMOS logic process. Key features of the product-like Macro are dual power supply with input voltage fluctuations, wide operating temperature range from -40ºC to 150ºC, fast byte/word program under 10s and sector/chip erase under 10ms. The macro random read access time is only 8ns under worst case conditions. Key process monitors are characterization and yield of the Macro. Endurance was extended to 200k cycles and satisfy automotive grade requirement with wide read margin. Post-cycling data retention performs very well up to 150ºC. Wafer sort yield is in high double digits, with consistent wafer-to-wafer and within-wafer uniformity, showing good process control. The technology is suitable for high-speed automotive MCU, as well as IoT, smart card, and industrial MCU applications.

Wire bonding, bumping & assembly related failures & improvements

In this paper, investigation of wire bonding, bumping and assembly related failures are performed using optical microscopy, secondary electron microscopy and transmission electron microscopy. Also, the understandings of the failures and root causes are presented. For example, corrosions caused by contaminant such as Fluorine and Cu precipitates on Al-Cu alloyed bond pads that lead to discolored or non-stick on pads problem are discussed. In addition, the formation of small bumps when oxide/silicon nitride passivation is employed and chipping at die edges caused during assembly that leads to open-circuit are studied. In conclusion, possible solutions of these failures are recommended to achieve robust assembly and packaging.