Roc Berenguer

A Fully Integrated 26.5 dBm CMOS Power Amplifier for IEEE 802.11a WLAN Standard with on-chip "power inductors"

A fully integrated power amplifier (PA) for 5 GHz 802.11a standard is implemented using a 0.18 mum CMOS process. In this paper we present the new concept of power inductors. These on-chip inductors are implemented on the transistor drains and the output network and they can withstand the high level current signals that go through them while presenting low DC-resistance and high Q characteristics. The two stage differential power amplifier is fully integrated including the input and output networks. Measurement results show that the power amplifier achieves a power gain of 25.5 dB, 1 dB compression point (P1dB) of 20.8 dBm and power added efficiency of 26.7 %. The saturated output power is 26.5 dBm, achieving the highest reported output power among CMOS PAs for 5-GHz WLAN applications

A MM-Wave Configurable VCO Using MCPW-Based Tunable Inductor in 65-nm CMOS

This paper describes the modeling and the design of a ladder-structured multilayer-coplanar-waveguide-based tunable differential inductor with wide tuning range and high quality factor. The impacts of process variation on the performance of the inductor and active components are mitigated through postfabrication tuning. A configurable 77-GHz voltage-controlled oscillator (VCO) with a tunable inductor has been designed and implemented in a 65-nm single-poly six-metal bulk CMOS technology. Techniques for tuning the center frequency and increasing the tuning range are described. Under a 1.5-V supply, the measured VCO can be tuned from 67.3 to 77.9 GHz, i.e., 15.8%, while consuming 14.3 mW; the output power is -4.5 dBm, and the phase noise at a 10-MHz offset from the 77-GHz carrier is -108.4 dBc/Hz. This configurable VCO provides a wide tuning range and immunity to process variation.

Battery-free wireless sensors for industrial applications based on UHF RFID technology

This work provides an overview of the current state-of-the-art of the RFID technology in the Wireless Sensor Network (WSN) field. The different RFID alternatives are described with their pros and cons. The benefits and limitations of battery-free wireless sensors based on RFID technology are presented. Subsequently, the paper describes the design of an UHF RFID integrated circuit (IC) designed to harvest and store the power from an incoming RF signal in order to supply low power analog or digital sensors. The IC has been implemented using a low cost 0.35 μm CMOS process and it incorporates a serial peripheral interface (SPI) in order to communicate with the sensor. Battery-free wireless operation for industrial monitoring using the designed IC has been demonstrated by implementing two wireless sensors that monitor both temperature, using a thermistor, and pressure, using a commercial digital sensor. The wireless temperature sensor shows an error below ±1°C from -25°C to 105°C, whereas the pressure sensor error is below ±2 mbar from 325 to 1000 mbar. A battery free communication range of 1.5 meters is demonstrated for both sensors using a 2-W effective radiated output power reader.

A Dual-Gain ESD-protected LNA with Integrated Antenna Sensor for a Combined GALILEO and GPS front-end

This paper presents a dual-gain ESD protected LNA with integrated antenna sensor for a combined GPS and GALILEO front-end. The amplifier has been implemented using a standard 0.35mum SiGe BiCMOS process and the total power consumption is only 8 mA from a 3 V supply. It provides a power gain of 18 dB and a low noise figure of 3.3 dB working in the high gain mode of operation, which makes this LNA suitable for high sensitivity applications such as the new generation of positioning services

Low power voltage limiter design for a full passive UHF RFID sensor

This paper presents a low power voltage limiter design that avoids possible damages in the circuits of the analog front-end of the RFID sensor due to voltage surges whenever reader and tag are very close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator in order to provide low temperature and process deviation of the limiting voltage. The measured limiting voltage is 2.9V with a voltage variation of only +/−0.025V for the four measured dies. The current consumption is only 150nA when the reader and the tag are far away one to each other, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35µm CMOS technology.

Wireless patient monitorization using full passive devices

There is a strong motivation for the implementation of electronic identification systems and wireless sensors in hospitals. This work presents a sensor enabled passive RFID tag for patient monitorization. Special attention is paid to the analog FE, which has been designed and implemented in a low cost 0.35µm CMOS standard process. The proposed front-end architecture allows the implementation of power management techniques that, together with the power optimized blocks and the use of Schottky diodes in the voltage multiplier, achieves a long reading range. The fabricated analog front-end, assembled to a matched dipole antenna, is able to provide a wireless communication up to 2.4m from a 2W EIRP output power reader to a digital module+sensor with an average power consumption up to 37.5µW. The system has been tested with a temperature sensor. Successful ID and temperature communication with a commercial RFID reader over a distance of approximately 2m has been reported. The results demonstrate the capacity of the proposed system for wireless patient monitorization.

A low power low noise figure GPS/GALILEO front-end for handheld applications in a 0.35 /spl mu/m SiGe process

A highly integrated, low power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 mum SiGe process. It has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4 MHz approximately. The front-end exhibits a voltage gain of 103 dB and present a SSB noise figure of 3.7 dB which makes it suitable for high sensitivity applications. The achieved power consumption is only 62 mW from a 3V voltage supply with no compromise with performance and with a minimal amount of external components

A Wideband and High-Linearity E -B and Transmitter Integrated in a 55-nm SiGe Technology for Backhaul Point-to-Point 10-Gb/s Links

This paper presents the design of a wideband and high-linearity

A 15–21 GHz I/Q Upconverter With an On-Chip Linearization Circuit for 10 Gbps mm-Wave Links

E

Implementation of a zero-second-IF transmitter for wide-band millimeter-wave links

-band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16–21-GHz IF signal to the 71–76- and 81–86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71–76- and 81–86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future high-capacity backhaul and fronthaul point-to-point links.