Juan Lanchares

Annealing placement by thermodynamic combinatorial optimization

Placement is key issue of integrated circuit physical design. There exist some techniques inspired in thermodynamics coping with this problem as Simulated Annealing. In this article, we present a combinatorial optimization method directly derived from both Thermodynamics and Information Theory. In TCO (Thermodynamic Combinatorial Optimization), two kinds of processes are considered: microstate and macrostate transformations. Applying the Shannons definition of entropy to reversible microstate transformations, a probability of acceptance based on Fermi--Dirac statistics is derived. On the other hand, applying thermodynamic laws to macrostate transformations, an efficient annealing schedule is provided. TCO has been compared with a custom Simulated Annealing (SA) tool on a set of benchmark circuits for the FPGA (Field Programmable Gate Arrays) placement problem. TCO has provided the high-quality results of SA, while inheriting the adaptive properties of Natural Optimization (NO).

RSR: a new rectilinear Steiner minimum tree approximation for FPGA placement and global routing

The work combines FPGA placement and global routing phases in a single phase, taking advantage of the interrelations between them both. The authors have developed rectilinear Steiner regions (RSR), a new fast algorithm to approximate the rectilinear Steiner minimum tree (RSMT) of each multi-terminal net. The search of placement solutions is performed in three simulated annealing optimization phases, guided by different objective functions. The first one uses a semi-perimeter classic metric to reduce the length of the nets. The second one estimates more precisely the length of the nets with RSR algorithm. The third stage measures the congestion making a fast routing of RSR regions in each placement iteration. They have also developed an RSR-based global router. This optimization method has been applied for the placement and global routing of a set of benchmark circuits. The layouts obtained, require equal or fewer routing tracks per channel segment than those produced by other tools appeared in the literature, that only optimize the semi-perimeter classic placement cost function.

Functional partitioning for hardware-software codesign using genetic algorithms

Hardware-software partitioning is one of the most important issues of codesign of embedded systems because it is made at the beginning of the cycle of design. In terms of costs and delays, final results will strongly depend on partitioning. In this work we address the functional partitioning problem of hardware-software codesign using a genetic algorithm. Experimental results includes a comparative study with three algorithms: simulated annealing, Fiduccia-Matheyses and a modified version of this with an improvement of results.

Is the island model fault tolerant

In this paper, we present a study on the fault tolerance nature of the island model when applied to Genetic Algorithms. Parallel and distributed models have been extensively applied to GAs when researchers tackle hard problems. The idea is both to reduce computing time while also improving diversity of populations and therefore quality of solutions. Nevertheless, there are few works dealing with the problem of faults that are usually present when a distributed infrastructure is employed for running the parallel algorithm. This paper studies the behavior of the Island Model when faults appear on a parallel computer or a network of computers. Two benchmark problems have been employed, and good results obtained for each of them allow us to reliably consider Island Model as a fault tolerant parallel algorithm.

A parallel compact genetic algorithm for multi-FPGA partitioning

In this paper we investigate the design of a compact genetic algorithm to solve multi-FPGA partitioning problems. Nowadays Multi-FPGA systems are used for a great variety of applications such as dynamically reconfigurable hardware applications, digital circuit emulation, and numerical computation. Both a sequential and a parallel version of a compact genetic algorithm (cGA) have been designed and implemented on a cluster of workstations. The peculiarities of the cGA permits to save memory in order to address large multi-FPGA partitioning problems, while the exploitation of parallelism allows to reduce execution times. The good results achieved on several experiments conducted on different multi-FPGA partitioning instances show that this solution is viable to solve multi-FPGA partitioning problems.

Hybrid parallelization of a compact genetic algorithm

Genetic algorithms (GAs) are stochastic optimization heuristics in which searches in solution space are carried out by imitating the population genetics stated in Darwins theory of evolution. We have focused this work on compact genetic algorithms (cGAs), which unlike standard GAs do not manage a population of solutions but only mimics its existence. We study several approaches that can be used to implement parallel cGAs in order to reduce the execution times and to improve the quality of the solutions reached by increasing population sizes. The parallelization models adopted to implement GAs can be classified as: centralized, global, fine grained and coarse grained. For a cGA, only the two first models can be applied. Our approach consists of a hybrid model which combines both centralized and global implementations. The cGA incorporates a local search method and has been applied for solving a graph-partitioning problem for solving the Multi-FPGA systems partitioning and placement.

Dynamic capacity-speed tradeoffs in SMT processor caches

Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phases within the same application, may require a different capacity-speed tradeoff. This problem is exacerbated in a Simultaneous Multi-Threaded (SMT) processor where the optimal cache design may vary drastically with the number of running threads and their characteristics. We propose to make this capacity-speed cache tradeoff dynamic within an SMT core. We extend a previously proposed globally asynchronous, locally synchronous (GALS) processor core with multi-threaded support, and implement dynamically resizable instruction and data caches. As the number of threads and their characteristics change, these adaptive caches automatically adjust from small sizes with fast access times to higher capacity configurations. While the former is more performance-optimal when the core runs a single thread, or a dual-thread workload with modest cache requirements, higher capacity caches work best with most multiple thread workloads. The use of a GALS microarchitecture permits the rest of the processor, namely the execution core, to run at full speed irrespective of the cache speeds. This approach yields an overall performance improvement of 24.7% over the best fixed-size caches for dual-thread workloads, and 19.2% for single-threaded applications.

Partitioning and placement for multi-FPGA systems using genetic algorithms

One of the most important and difficult tasks in multi-FPGA systems design is partitioning. The main problems are related to the I/O pins and logic capacity of FPGAs. The number of pins available is a critical problem, because FPGA devices have such a reduced number of them compared with their logic capacity. In addition we must reserve some of the pins to interconnect parts of the circuit placed on non-adjacent FPGAs. Most of the previous works have been adapted from other VLSI areas, and hence, they disregard the specific features of these kind of circuit. A new method for solving the partitioning and placement problem in multi-FPGA systems is presented. We use graph theory to describe the circuit, then a classical genetic algorithm (GA) is applied with a problem-specific encoding. The algorithm preserves the original structure of the circuit and by means of a fuzzy technique it evaluates the I/O-pins consumption due to direct and indirect connections between FPGAs. We have used the Partitioning93 benchmarks described with the Xilinx Netlist Format (XNF). The results obtained show how genetic algorithms are capable of accomplishing successfully the partitioning and placement tasks while respecting the board constraints.

Parallel Architectures and Bioinspired Algorithms

This monograph presents examples of best practices when combining bioinspired algorithms with parallel architectures. The book includes recent work by leading researchers in the field and offers a map with the main paths already explored and new ways towards the future. Parallel Architectures and Bioinspired Algorithms will be of value to both specialists in Bioinspired Algorithms, Parallel and Distributed Computing, as well as computer science students trying to understand the present and the future of Parallel Architectures and Bioinspired Algorithms.

Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems

Modern multimedia application exhibit high resource utilization. In order to efficiently run this kind of applications in embedded systems, the dynamic memory subsystem needs to be optimized. A key role in this optimization is played by the dynamic data structures that reside in every real-life application. This paper presents a novel and automated way to optimize dynamic data structures. The search space is pruned using genetic algorithms that converge to the best multilayered data structure implementation for the targeted applications.